CYIL1SN3000AA-GZDC Cypress Semiconductor Corp, CYIL1SN3000AA-GZDC Datasheet
CYIL1SN3000AA-GZDC
Specifications of CYIL1SN3000AA-GZDC
Related parts for CYIL1SN3000AA-GZDC
CYIL1SN3000AA-GZDC Summary of contents
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... Intelligent traffic system ■ Medical imaging ■ Industrial imaging Ordering Information Marketing Part Number CYIL1SN3000AA-GZDC Mono micro lens with glass CYIL1SE3000AA-GZDC Color micro lens with glass CYIL1SN3000-EVAL Mono micro lens demo kit Cypress Semiconductor Corporation Document Number: 001-44335 Rev. *C PRELIMINARY ...
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... Software FPN correction ................................................46 Off Chip PRNU Correction .............................................47 Package Information ...........................................................50 Pin Definitions ................................................................50 Pin Assignment ..............................................................55 Mechanical Specifications ..............................................57 Package Diagram ...........................................................58 Glass Lid ........................................................................60 Handling Precautions ..........................................................60 Limited Warranty .................................................................60 Return Material Authorization (RMA) .............................60 Document History Page ....................................................61 Sales, Solutions, and Legal Information ...........................61 Worldwide Sales and Design Support ............................61 CYIL1SN3000AA Page [+] Feedback ...
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... Parameter Conversion gain Full well charge Sensitivity Fill factor Parasitic light sensitivity < 1/5000 Dark noise FPN PRNU Dark signal Power dissipation Description CYIL1SN3000AA Specifications - 39.2 µV/e at the output - 27000e 2 1270 V.m /W.s at 600 nm with microlens 36% - 21e 37% at 680 nm with micro lens ...
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... Clock enabled, lux=0 ROT Clock enabled, lux=0 Clock enabled, lux=0 transient duration: 200ns Clock enabled, lux=0 Clock enabled, lux=0 Clock enabled, bright transient duration: 50ns (Refer toTable 43 on page 31) CYIL1SN3000AA Min Typ Max Units -5% 2.5 + 100 mA -5% 2 ...
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... PRECHARGE_BIAS_2 must be left floating because it is intended for testing purposes RES_DS ADC pix , V LVDS Comment . Decouple to GND decoupling ADC . Decouple to Vpix with PIX CYIL1SN3000AA Min Typ Max 0.8 1.1 1.4 Typ Max 206 485 Table 7 higher frame rates, the voltage Related Module ...
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... Figure 2 shows the spectral response of the mono and color versions of the LUPA 3000. Figure 3 on page 7 depicts the behavior of the micro lens for mono and color image sensor. Figure 2. Mono and Color Spectral Response CYIL1SN3000AA Page [+] Feedback ...
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... The AFE prepares the signal for the digital data block when the data is multiplexed and prepared for the LVDS interface. Note In Figure 6 on page 8, 32 pixels (1 kernel) are read out, where the MSB bit is the first bit out. CYIL1SN3000AA Page [+] Feedback ...
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... Document Number: 001-44335 Rev. *C PRELIMINARY Figure 5. Sensor Floor Plan On chip drivers Pixel kernels Pixel array 1696 * 1710 Pixel (0,0) Column amplifiers Odd kernels 32 Even kernels X-shift register 64 ADC’ LVDS drivers Figure 6. Column Multiplexing Scheme CYIL1SN3000AA Page [+] Feedback ...
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... A latency (delay) is incurred for the analog signal processing, PGA, and ADC stages. The total latency is 44 high speed input clock delays. The output synchronization signals from the LVDS “sync” channel factor in this latency. CYIL1SN3000AA Figure 8. Vrefp Vrefp Vrefp Vrefp ...
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... Vrefp - Vrefm (can be overdriven as a pair) ■ Vcm ■ Vdark capacitor matching. ■ Internal bandgap voltage Table 10 summarizes the ADC and AFE (signal processing) parameters. CYIL1SN3000AA Table 9 provides Vrefp-Vrefm Comments Gain Level (typ) 0 0.5x Maximum effective gain +6.0 dB (2x) 1 0.67x 0 ...
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... This is the default (POR) value. Bit 1 of this register allows calculation and insertion of a CRC checksum to the “synchronization” channel. No checksum is attached by default CYIL1SN3000AA Comment 9, the CRC value is calculated for each row msb Page [+] Feedback ...
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... These settings may require the use of nonstandard termination resistance. Current drive programming is accomplished using bits 3:0 of SPI register 72 (decimal – LVDS trim). Figure 11 on page 13 defines the programmable LVDS output current settings. CYIL1SN3000AA Page [+] Feedback ...
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... Clock Edge Adjust Register (b1000001 / d65) programming details. Cypress provides default settings for the programmable delay. These settings allow correct operation; there is no need to change these settings (unless for testing). CYIL1SN3000AA Comments Low power range Standard range Extra drive current to accommodate high ...
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... Table 11 on page 15. Document Number: 001-44335 Rev. *C PRELIMINARY mission over all channels accumulating to an aggregate guaranteed data rate of 13.6 Gbps. The transmission medium can be PCB traces, backplanes, or cables with a characteristic impedance of approximately 100 Ω. Figure 12. Overview of LVDS Setup CYIL1SN3000AA Page [+] Feedback ...
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... This is from LVDS point of view, from sensor point of view fMIN is 4 MHz (about 10 fps). At lower speeds dark current and storage node leakage starts influencing the image quality. Document Number: 001-44335 Rev. *C PRELIMINARY Specification (guaranteed by design) Description Specification (guaranteed by design Description CYIL1SN3000AA Units Min Typ Max 247 350 454 50 1 ...
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... ADC range. 3 bit SPI trim settings 1x, 0.95x, 0.91x, 0.83x, 0.77x, 0.71x, 0.67x, 0.5x. External power supply voltage. Requires gnd. Refer to Table 43 on page 31. Must pull down to gnd with ~ 50 kΩ. Five settings at ~ 1.2% adjust per step. CYIL1SN3000AA Table 13 overviews primary parameters Comment Page [+] Feedback ...
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... Biasing of first column amplifier Biasing of the output column amplifier Biasing of image core Biasing for column precharge structure Biasing for analog output amplifier Biasing of image core Biasing of y decoder Biasing of x decoder Fixed, read only register Chip revision number CYIL1SN3000AA Description Page [+] Feedback ...
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... Power down dark reference driver Power down voltage references Power down common mode voltage Spare Spare Test pattern for channel 0 Test pattern for channel 1 Test pattern for channel 2 Test pattern for channel 3 Test pattern for channel 4 Test pattern for channel 5 CYIL1SN3000AA Description Page [+] Feedback ...
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... This mode allows increasing the frame rate at a possibly reduced dynamic range. The reduction in dynamic range depends on the length of the ROT . / d1)” on page 20. The default timing is in reduced ROT mode, so there is no reduction in dynamic range. CYIL1SN3000AA Description See “ROT_timer (b0000001 Page [+] Feedback ...
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... ROT length is <N+2> sensor clocks (<N+2>*4 master clocks) where N is the register value On startup 00111 (9 sensor clocks) Document Number: 001-44335 Rev. *C PRELIMINARY column lines at the start of every ROT. Changing these bits does not change the total ROT length. . Effect Effect CYIL1SN3000AA ROT Pin on page 42 Bits <7:5> are ignored. Page [+] Feedback ...
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... FOT length is <N*4+2> sensor clocks (<N*4+2>*4 master clocks), where N is the register value On startup 00101000 Document Number: 001-44335 Rev. *C PRELIMINARY Effect Effect Effect Effect CYIL1SN3000AA Frame Overhead Time on Frame Overhead Time on page Frame Overhead Time on page 41. Frame Overhead Time on page FOT Pin on page 42 ...
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... Value bit<4:0> 00000 X readout starts with the first kernel (column 0) 00001 X readout starts with the third kernel (column 64) 11010 X readout starts with the fifty third kernel (column 1664) On startup 00000 Document Number: 001-44335 Rev. *C PRELIMINARY Effect Effect Effect Effect CYIL1SN3000AA Page [+] Feedback ...
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... Lower dark level Bias current changes 1.56 µA per LSB. Bits <7:6> are ignored. Table 27. Bias_col_load Register Value (Bit<5:0>) 000000 Bias current is 0A … 111111 Maximum bias current On startup 001000 (13.6 µA) Document Number: 001-44335 Rev. *C PRELIMINARY Effect Effect Effect CYIL1SN3000AA Page [+] Feedback ...
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... Table 29. Biasing_2 Register Value Bias_sel_pre, bits<3:0> 0000 Bias current is 0A … 1111 Maximum bias current On startup 0111 (~ 500 µA) Bias_analog_out, bits<7:4> 0000 Bias current is 0A … 1111 Maximum bias current On startup 0111 Document Number: 001-44335 Rev. *C PRELIMINARY Effect Effect CYIL1SN3000AA Page [+] Feedback ...
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... This register contains the Start Of Frame (SOF) keyword. Table 33. SOF Register On startup SOL (b0100001 / d33) This register contains the Start Of Line (SOL) keyword. Table 34. SOL Register On startup Document Number: 001-44335 Rev. *C PRELIMINARY Effect Effect Effect Value 00100000 Value 00100010 CYIL1SN3000AA Page [+] Feedback ...
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... On startup Document Number: 001-44335 Rev. *C PRELIMINARY Value 00100011 Value 11101011 Value 11101011 on page 16. Effect R2= 82.5K R2= 83.5K R2= 84.5K Vbg 1.25 Vnominal R2= 85.5K R2= 86.5K 010 0.50x 0.67x 0.71x 0.77x 0.83x 0.91x 0.95x 1.00x nominal 111 CYIL1SN3000AA Page [+] Feedback ...
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... CLK_SEQ 0000 DLY_SEQ = 0001 0111 1111 Document Number: 001-44335 Rev. *C PRELIMINARY LUPA 3000 Internal Clocking Figure 13. DATA(N+1) DATA(N) DATA(N+ CYIL1SN3000AA Figure 13 shows DATA(N-1) DATA( DATA(N+ Page [+] Feedback ...
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... CLK_SEQ is +1 clk edge after falling edge of CLK_ADC 0010 +2 0011 +3 0100 +4 0101 +5 0110 +6 0111 +7 1000 Same as code 0000 1001 CLK_SEQ is -1 clk edge before falling edge of CLK_ADC 1010 -2 1011 -3 1100 -4 1101 -5 1110 -6 1111 -7 On startup 1100 Document Number: 001-44335 Rev. *C PRELIMINARY Effect Effect CYIL1SN3000AA Page [+] Feedback ...
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... ADCs for testing. When set, the external pin Analog_in and Vdark reference are sent to all ADCs. sblk_spare1, bit<6>. This bit is a spare control bit set to ■ POR. sblk_spare2, bit<7>.: This bit is a spare control bit set to ■ POR. Effect CYIL1SN3000AA Page [+] Feedback ...
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... ADC dynamic range to the pixel voltage range. The startup value for this register is b000, which corresponds to a unity gain (1x). Refer to the section Programmable Gain Amplifiers Document Number: 001-44335 Rev. *C PRELIMINARY Effect on page 9 for information on the control bit to gain setting table relationship. CYIL1SN3000AA LVDS Data Page [+] Feedback ...
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... Power down vrefp/vrefm references On startup 0 pwd_vcm, bit<5> 1 Disable on-chip VCM generation. Apply 0.9V to Vcm pin 87 and decouple to ground with 10 nF capacitor. On startup 0 sblk_spare3, bit<6> 0 Normal operation 1 On startup 0 sblk_spare4, bit<7> Normal operation On startup 1 Document Number: 001-44335 Rev. *C PRELIMINARY Table 43. Effect CYIL1SN3000AA Page [+] Feedback ...
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... Document Number: 001-44335 Rev. *C PRELIMINARY Startup Value b00000001 b00000001 b00000010 b00000010 b00000100 b00000100 b00001000 b00001000 b00010000 b00010000 b00100000 b00100000 b01000000 b01000000 b10000000 b10000000 b10000000 b10000000 b01000000 b01000000 b00100000 b00100000 b00010000 b00010000 b00001000 b00001000 b00000100 b00000100 b00000010 b00000010 b00000000 b00000000 CYIL1SN3000AA Page [+] Feedback ...
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... The read operation is terminated by raising the CS pin. The maximum operating frequency is 10 MHz. Note SPI settings cannot be uploaded during readout. Figure 14. SPI Read Timing Figure 15. SPI Write Timing CYIL1SN3000AA Page [+] Feedback ...
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... Frame Rate =485 FPS Alternatively, frame rate can also be expressed in terms of reset length and Integration time rather than readout time. The sequence of events shown in integration and readout in pipelined global shutter mode. CYIL1SN3000AA Comment Clarification Row Overhead The ROT transfers the pixel Time output to the column amplifiers ...
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... Sequencer reset, active LOW Input System clock (206 MHz) Input SPI chip select Input SPI clock Input Data line of the SPI, serial input Data line of the SPI, serial output CYIL1SN3000AA Frame Rate Frame Period(ms) (fps) 484 2.065 712 1.404 1001 1.000 2653 0 ...
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... The pixels are selected in groups of 32 (kernel). The internal timing is generated by the sequencer. LUPA3000 works in slave mode, the integration timing is directly controlled over two external pins (Exposure 1 and Exposure 2) but the readout timing is still controlled by the sequencer. Figure 19. Global Readout Timing CYIL1SN3000AA Page [+] Feedback ...
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... The possible applications for this triggered shutter mode are: ■ Synchronize external flash with exposure ■ Apply extremely long integration times Exposure Time FOT Reset FOT Readout N CYIL1SN3000AA FOT Reset Readout FOT N+1 N+1 Page [+] Feedback ...
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... The active area read out by the sequencer in full frame mode is shown in Figure 22 shows the behavior of the data and sync channels. Document Number: 001-44335 Rev. *C PRELIMINARY Figure 21. Pixels are always read in multiples of 32. Figure 21. Sensor Read Out Format Figure 22. Data and Sync Channel Behavior CYIL1SN3000AA Page [+] Feedback ...
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... The falling edge of pix_sample is a fixed amount of time after the falling edge of EXPOSURE_1. This time is set SAMPLE_TIMER (see Frame Overhead Figure 24. High Level Readout Timing wait till ROT integration time CYIL1SN3000AA shows a high level timing; ‘Lx’ refers to Time). FOT SAMPLE_TIMER Page [+] Feedback ...
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... The sync channel transmits programmable keywords to allow frame and line synchronization. When not transmitting data from the ADC, the data channels transmit the toggling Idle_A and Idle_B words result, the data stream from the sensor has a fixed format. CYIL1SN3000AA wait till ROT FOT ...
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... FOT_TIMER arrives typically 500 ns after VMEM_TIMER. The rising edge of pixel_reset coincides with the rising edge of pixel_vmem. Figure 28. FOT Timing VMEM_TIMER PRECHARGE_TIMER SAMPLE_TIMER FOT_TIMER invalid data CYIL1SN3000AA on page 40. The data stream is still valid. depending on ROT depending on ROT EOL Ix Ix SOL a< ...
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... During the chip reset the data on the LVDS outputs (data channels and sync channel) is invalid. When the chip comes out of reset, but the sequencer is kept in reset, the LVDS outputs toggle between the idle words. CYIL1SN3000AA 29. Rise and Fall Times (20 pF Load) ...
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... Set RESET_N_SEQ register bit to zero if other SPI registers need to be uploaded. 4. Set the RESET_N_SEQ bit all required SPI registers are changed. LUPA 3000 operates only in slave mode; therefore, the sensor is now controlled through the EXPOSURE_1 pin. CYIL1SN3000AA FOT+ROT valid data valid data Page [+] Feedback ...
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... Document Number: 001-44335 Rev. *C PRELIMINARY Figure 33. Sequence of Data from LUPA 3000 CYIL1SN3000AA Page [+] Feedback ...
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... By choosing the time stamps of the double slope resets (typical at 90%, configurable by the user possible to have a nonsat- urated pixel value even for pixels that receive a huge amount of light. The reset levels are configured through external (power) pins. CYIL1SN3000AA Figure 35 repre- Page [+] Feedback ...
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... Use an averaged dark image to calibrate FPN, this eliminates other noise sources that would be present in the dark image. ■ Use a different dark image to calibrate for different operation conditions. Different operation conditions can be changes in temperature, FOT and ROT timing, and gain settings. CYIL1SN3000AA Page [+] Feedback ...
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... Adjust the black level with the help of histogram by modifying DAC offset. 2. Store a dark image by closing the lens aperture, but make sure no value is absolute zero. Document Number: 001-44335 Rev. *C PRELIMINARY 3. Subtract the dark reference image from all the captured images. CYIL1SN3000AA Page [+] Feedback ...
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... Gn - data of a pixel before carrying out a calibration Bn - black calibration data of the pixel Wn - white (Gray) calibration data of the pixel The image with both FPN and PRNU correction is shown in Figure 39. Note that no FPN lines are present in this image even in saturated regions. CYIL1SN3000AA Page [+] Feedback ...
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... Figure 39. Image after FPN and PRNU Correction Note Dark and bright images needs to be updated whenever gain settings, ROT, FOT and temperature of the sensor are changed. Document Number: 001-44335 Rev. *C PRELIMINARY CYIL1SN3000AA Page [+] Feedback ...
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... LVDS data output Outp 12 LVDS data output Outn 12 LVDS data output Vlvds 2.5 V LVDS GNDlvds Ground LVDS Outp 13 LVDS data output Outn 13 LVDS data output Outp 14 LVDS data output Outn 14 LVDS data output Outp 15 LVDS data output CYIL1SN3000AA Description Page [+] Feedback ...
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... LVDS data output Outn 29 LVDS data output Outp 30 LVDS data output Outn 30 LVDS data output Outp 31 LVDS data output Outn 31 LVDS data output Clk_inp LVDS input clock Clk_inn LVDS input clock Syncp LVDS sync channel Syncn LVDS sync channel CYIL1SN3000AA Description Page [+] Feedback ...
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... Exposure 1 Digital input Exposure 2 Digital input ROT Digital output FOT Digital output Not Assigned Not assigned Current_Ref_1 Current reference resistor Not Assigned Not assigned Analog_Out Analog output (leave floating) Not Assigned Not assigned Not Assigned Not assigned CYIL1SN3000AA Description Page [+] Feedback ...
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... Vmem low supply (typically 2.5 V) Vmem_h Vmem high supply (typically 3.3 V) Vprecharge Pix precharge supply D/A Ground Die attach ground Vdd 2.5 V digital Not Assigned Not assigned GNDdrivers Ground array drivers Vres_ds Reset DS supply (typically 2.5 V) Vres Reset suppy (typically 3.3 V) CYIL1SN3000AA Description Page [+] Feedback ...
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... Vpix (typically 2.5 V) Vaa 2.5 V analog GNDa Ground analog Vaa 2.5 V analog Vaa 2.5 V analog GNDa Ground analog GNDa Ground analog Vaa 2.5 V analog Vaa 2.5 V analog GNDa Ground analog GNDa Ground analog GNDa Ground analog Vdd 2.5 V digital CYIL1SN3000AA Description Page [+] Feedback ...
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... D/A Ground Die attach ground D/A Ground Die attach ground D/A Ground Die attach ground Non Assigned Pins Pins that are marked “not assigned” in the pin list must be left floating. Some of them are used by Cypress for debugging. CYIL1SN3000AA Description Page [+] Feedback ...
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... CYIL1SN3000AA Signal Groups 175 174 172 LVDS Data Output 176 173 171 Not Assigned 169 170 Die Attach Ground 168 167 Supply LVDS ...
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... Lead-free wave soldering profile for pin grid array package if no socket is used Recommended socket manufacturer Andon Electronics (http://www.andonelectronics.com) Document Number: 001-44335 Rev. *C PRELIMINARY Min -1 -1 -50 -1 400 20 BGA Socket: 10-21-06-369-414T4-R27-L14 Thru Hole: 10-21-06-369-400T4-R27-L14 CYIL1SN3000AA Typ Max Units 750 µm 0 µm 0 µ deg 0 1 ...
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... Package Diagram Figure 41. LUPA 3000 µPGA Package Diagram (Top View) INDEX MARK (PLATING OPTION) 4X (0.50X45°) CHAMFER Document Number: 001-44335 Rev. *C PRELIMINARY +0.29 GLASS PIN Fe-Ni-Co ALLOY CYIL1SN3000AA 4X (R 0.20) 0.15 001-54817 *A 369X Page [+] Feedback ...
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... Figure 42. LUPA 3000 µPGA Package Diagram (Bottom View) 369X 4X (0.25X45°) CHAMFER Document Number: 001-44335 Rev. *C PRELIMINARY (AT PIN BASE) (AT PIN BASE 369X Ø0.97 CYIL1SN3000AA ALUMINA COAT Page [+] Feedback ...
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... ESD-safe shipping containers. Products returned to Cypress for failure analysis should be handled under these same conditions and packed in its original packing materials, or the customer may be liable for the product. CYIL1SN3000AA Page [+] Feedback ...
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... Document History Page Document Title: CYIL1SN3000AA, LUPA 3000: 3 MegaPixel High Speed CMOS Sensor Document Number: 001-44335 Orig. of Revision ECN Change ** 2732454 NVEA/PYRS *A 2756217 NVEA *B 2899662 VDS *C 2934992 NVEA Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress offers standard and customized CMOS image sensors for consumer as well as industrial and professional applications. ...