CYII4SD1300AA-QDC Cypress Semiconductor Corp, CYII4SD1300AA-QDC Datasheet
CYII4SD1300AA-QDC
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CYII4SD1300AA-QDC Summary of contents
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... This is combined with an on-chip double sampling technique to cancel fixed pattern noise. Ordering Information Marketing Part Number CYII4SM1300AA-QDC CYII4SM1300AA-QWC CYII4SD1300AA-QDC Cypress Semiconductor Corporation Document Number: 38-05707 Rev. *C IBIS4-1300 1.3 MPxl Rolling Shutter Features SXGA resolution: 1280 x 1024 pixels ■ ...
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Architecture of Image Sensor 1280 x 1024 pixel array The IBIS4-1300 is an SXGA CMOS image sensor. The chip is composed of 3 modules: an image sensor core, a programmable gain output amplifier, and an on-chip 10 bit ADC. Figure ...
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Image Sensor Core – Focal Plane Array The core of the sensor is the pixel array with 1280 x 1024 (SXGA) active pixels. The name 'active pixels' refers to the amplifying element in each pixel. Next to the pixel array ...
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Table 1. Optical and Electrical Characteristics (continued) Pixel Characteristics Table 1.1. In this table you find achievable values using the analog output. X pixelsY pixels X Freq X Clock # # Hz sec 1286 1030 1,00E+07 1,00E-07 1286 1030 2,00E+07 ...
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Table 1. Optical and Electrical Characteristics (continued) Pixel Characteristics Anti-blooming Smear Note 3. Peak noise photons are defined as (noise electrons) / (FF*peak QE). Features and General Specifications Electronic shutter Viewfinder mode Digital output Color filter array Die size Package ...
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Figure 3. shows the spectral response characteristic. The curve is measured directly on the pixels. It includes effects of non-sensitive areas in the pixel, e.g., interconnection lines. The sensor is light sensitive between 400 and 1000 nm. The peak QE ...
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Color Sensitivity 2.00E+05 1.80E+05 1.60E+05 1.40E+05 1.20E+05 1.00E+05 8.00E+04 6.00E+04 4.00E+04 2.00E+04 0.00E+00 400 500 Charge Conversion – Conversion of Electrons in an Output Signal Figure 5. IBIS4-1300 Response Curve – Two Pixels – Lowest Gain Setting (0000) 1,2 1 ...
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Figure 5. shows the pixel response curve in linear response mode. This curve is the relation between the electrons detected in the pixel and the output signal. This curve was measured with light of 600 nm, with an integration time ...
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Table 2. Pins of the Image Sensor Core (continued) Digital Controls Power and Ground VDD_RESETL 59 VDD_RESETR 79 VDD_ARRAY 55 VDD GND Output Amplifier The output amplifier stage is user-programmable for gain ...
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Vhigh_dac offset [0..3] Vlow_dac Figure 6. shows the architecture of the output amplifier. First of all, there is a multiplexer which selects either the imager core signal or an external pin EXTIN as the input of ...
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Figure 7. Offset Adjustment: Fast Offset Adjustment Mode calib_f dark signal unitygain > 100 ns There are 2 modes of offset calibration for the output amplifier: slow and fast adjustment. Figure 7. shows the timing and signal waveforms for fast ...
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Table 4. Pins Involved in Output Amplifier Circuitry Name No. Analog Signals Extin 12 Output 13 Digital Controls Sel_extin 9 gc_bit0 17 gc_bit1 18 gc_bit2 19 gc_bit3 20 unitygain 21 calib_s 16 calib_f 22 dac_b0 26 dac_b1 25 dac_b2 24 ...
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Output Amplifier Gain Control 20,00 18,00 16,00 14,00 12,00 10,00 8,00 6,00 4,00 2,00 0, Table 5. DC Gain of Output Amplifier for Different Gain Settings Gain Setting DC Gain (<1 MHz) 0000 1.28 0001 1.51 0010 ...
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Figure 10. Output Amplifier Bandwidth for Different Gain Settings Unity Figure 11. Typical Transfer Characteristic of Output Amplifier (no Clipping, Voffset = ...
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Figure 11. shows the output characteristic curve in a typical case for the imager. The offset voltage is adjusted which corre- sponds to the low-level voltage of the ADC. Clipping is off, and the input signal is ...
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ADC Timing The ADC converts on the falling edge of the CLK_ADC clock. The input signal should be stable during a time Ts before the falling clock edge. The digital output is available Td after the falling clock edge (Figure ...
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Table 7. ADC Pins (continued) Name No. Reference Voltages VLOW_ADC 71 VHIGH_ADC 61 PBIASDIG1 64 PBIASENCLOAD 65 PBIASDIG2 66 NBIASANA2 69 NBIASANA 70 Power and Ground VDD_DIG 56, 76 VDD_AN 58, 74 GND_DIG 57, 75 GND_AN 60, 72 Control of ...
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Figure 14. shows the ADC transfer characteristic. For this measurement, the ADC input was connected to a 16-bit DAC. The input voltage was a 100 kHz triangle waveform. The non-linear ADC conversion is intended for gamma-correction of the images. It ...
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Operation of the Image Sensor Set Configuration and Pulse Timing Figure 15. Typical Operation Mode (Readout of a Frame) Set configuration - output offset - amplifier gain - viewfinder on/off - determine integration time of next frame Set flag to ...
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Set Configuration Configuration of the image sensor implies control and adjustment of the following points: output amplifier offset level, set by 'dac_bit[0...3]' ■ output amplifier gain setting, set by 'gc_bit[0...3]' ■ Viewfinder Mode Versus Normal Readout Table 8. Coordinate of ...
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Figure 16. Timing of Y Shift Registers (for Row Selection) Line n n- selected CLCK_Y SYNCY Min 25 ns Clock EOS End-of-Scan: EOS_YL, EOS_YR, EOS_X All three shift registers are equipped with 'end-of-scan' pulses. These pulses are low during the ...
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Figure 18. Timing Constraints for Row Readout Initialization (Blanking Time) SYNC_YL SYNC_YR Tc CLK_YR CLK YL SHY SIN RESET L/R SYNC_X CLOCK_X Table 9. Timing Constraints on Row Initialization Pulses Sequence Ta Min 0 Tc Min Typ. ...
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Figure 18. and Table 9. illustrate the timing constraints of the row initialization/ blanking sequence. The EOS_X pulse flags the end of the scanning of previous ■ line, and should be considered as a diagnostic means only. The blanking sequence ...
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Figure 20. Timing of X Shift Register and Pixels Readout DCREF on bus n-1 Output Clock Sync Min 25 ns On-Chip Generated Electrical Dark References The sensor outputs a electrical dark reference level after the 2nd falling edge on the ...
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Example: tIming Used on IBIS4 Breadboard The next figure is the timing as used in the IBIS4 breadboard version 12 January 2000. In this baseline only CALIB_F is used Figure 22. Pulse Sequence Used in IBIS4 Breadboard v. January 2000 ...
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Offset Level Adjustment The offset level of the output signal is set by a 4-bit digital word. The offset level voltage is selected between VLOW_DAC and VHIGH_DAC on 16 taps. Figure 24. Response Curve of the Pixels in Dual Slope ...
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Figure 26. Linear Short Exposure Time Figure 27. Double Slope Integration Document Number: 38-05707 Rev. *C CYII4SM1300AA Electrical Parameters Dc Voltages VDD and GND Nominal VDD-GND is 5V DC. Overall current consumption for the different parts. imager core + output ...
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Pin Configuration Pin List Signal Type Symbols A Analog D Digital W Word bit No. Name Type I/O 1 Nbiasarray pbias2 Pbias xmux_nbias Sync_yr clk_yr ...
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No. Name Type I/O 29 clk_x shy dccon dcref gnd vdd sin sync_y clk_yl D I ...
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No. Name Type I/O 63 tri_adc pbiasdig1 pbiasencload pbiasdig2 nonlinear n.c. 69 nbiasana2 nbiasana vlow_adc gnd_an ...
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Relative position of pads in corners: see the following figure ■ (measures in um). 150 393 468 474 Color Filter Geometry Sensors with diagonal pattern have: Pixel (1,1) is RED ■ First line sequence is BGRBGR ■ Second line sequence ...
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Package 84 pins ceramic LCC package (JLCC also available) ■ Standard 0.04 inch pitch outline ■ 0.46" square cavity ■ Pin1 568 m 1280,1024 11 12 Cover Glass Size 18x18 mm for JLCC and LCC ■ Color ...
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Figure 29. Transmission Characteristics of BG39 Glass Used as NIR Cut-Off Filter for IBIS4-1300 Color Image Sensors BG39 transmission characteristics 1 0,9 0,8 0,7 0,6 0,5 0,4 0,3 0,2 0,1 0 400 500 Monochrome Sensor Refractive index: 1,52 ■ Figure ...
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... Ordering Information Marketing Part Number CYII4SM1300AA-QDC CYII4SM1300AA-QWC CYII4SD1300AA-QDC FAQ 1000 100 0,1 The above graph is measured on an IBIS4-1300 under nominal operation, using breadboard. This particular sensor has about 100 "bad pixels" at RT. Average offset (=dark signal) and RMS (=FPN of dark signal) are measured versus temperature. Offset is referred to the " ...
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