MT9V135L12STCES Micron Technology Inc, MT9V135L12STCES Datasheet - Page 7

• Manufacturer Part Number: MT9V135L12STCES
• Manufacturer: Micron Technology Inc

Specifications of MT9V135L12STCES

• Lead Free Status / RoHS Status: Compliant

Table 4:
PDF: 09005aef82c99cd/Source:09005aef824c99db
MT9V135_LDS_2.fm - Rev. B 3/07 EN
5, 4, 3, 2, 1, 48,
Assignment
6, 7, 8, 9, 10,
11, 12, 13
15, 32, 37
47, 46
16, 36
Pin
27
26
14
20
44
45
42
41
43
35
33
31
39
38
29
28
30
34
40
Pin Descriptions (continued)
Notes:
FRAME_VALID
LVDS_ENABLE
LINE_VALID
D
D
LVDS_NEG
LVDS_POS
PEDESTAL
DAC_NEG
D
DAC_POS
DAC_REF
DIN_CLK
V
D
OUT
OUT
VAAPIX
V
PIXCLK
OUT
Name
DD
A
D
IN
S
DD
V
V
DATA
GND
GND
[7:0]
AA
DD
_LSB0
_LSB1
DAC
PLL
[7:0]
2. ALL ground pins (A
3. Inputs are not tolerant to signal voltages above 3.1V.
4. All unused inputs must be tied to GND or V
5. V
1. ALL power pins (V
(nominal). Power pins cannot be floated.
floated.
AA
and VAAPIX must be tied to the same potential for proper operation.
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Supply
Supply
Supply
Supply
Supply
Supply
Supply
Input
Input
Input
Input
Type
DD
GND
/V
If “0” at reset: Does not add pedestal to composite video output.
If “1” at reset: Adds pedestal to composite video output.
Valid for NTSC only, pull low for PAL operation.
Active HIGH: Enables the LVDS output port. Must be HIGH if LVDS is
to be used.
External data input port selectable at video encoder input.
D
Two-wire serial interface data I/O.
Pixel data output D
significant bit (LSB)). Data output [9:2] in sensor stand-alone mode.
Sensor stand-alone mode output 0—typically left unconnected for
normal SOC operation.
Sensor stand-alone mode output 1—typically left unconnected for
normal SOC operation.
Active HIGH: FRAME_VALID; indicates active frame.
Active HIGH: LINE_VALID, DATA_VALID; indicates active pixel.
Pixel clock output.
Positive video DAC output in differential mode.
Video DAC output in single-ended mode.
Negative video DAC output in differential mode.
External reference resistor for video DAC.
LVDS positive output.
LVDS negative output.
Analog ground.
Digital ground.
Analog power: 2.5V–3.1V (2.8V nominal).
Pixel array analog power supply: 2.5V–3.1V (2.8V nominal).
Digital power: 2.5V-3.1V (2.8V nominal).
DAC power: 2.5V-3.1V (2.8V nominal).
LVDS PLL power: 2.5V-3.1V (2.8V nominal).
DD
/D
IN
GND
DAC/V
capture clock. (This clock must be synchronous to CLK_IN.)
) must be connected to ground. Ground pins cannot be
7
DD
MT9V135: SOC VGA Digital Image Sensor
PLL/V
Micron Technology, Inc., reserves the right to change products or specifications without notice.
AA
/VAAPIX) must be connected to 2.8V
OUT
DD
7 (most significant bit (MSB)), D
.
Description
©2006 Micron Technology, Inc. All rights reserved.
Typical Connections
OUT
Preliminary
0 (least