54ABT16373W-QML National Semiconductor, 54ABT16373W-QML Datasheet

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54ABT16373W-QML

Manufacturer Part Number
54ABT16373W-QML
Description
Manufacturer
National Semiconductor
Type
D-Typer
Datasheet

Specifications of 54ABT16373W-QML

Logic Family
ABT
Number Of Bits
16
Number Of Elements
2
Latch Mode
Transparent
Polarity
Non-Inverting
Technology
BiCMOS
Package Type
CPAK
Propagation Delay Time
8.5ns
Operating Supply Voltage (typ)
5V
High Level Output Current
-24mA
Low Level Output Current
48mA
Operating Supply Voltage (min)
4.5V
Operating Supply Voltage (max)
5.5V
Operating Temp Range
-55C to 125C
Operating Temperature Classification
Military
Mounting
Surface Mount
Pin Count
48
Output Type
3-State
Lead Free Status / RoHS Status
Not Compliant
© 1998 National Semiconductor Corporation
54ABT16373
16-Bit Transparent Latch with TRI-STATE
General Description
The ABT16373 contains sixteen non-inverting latches with
TRI-STATE outputs and is intended for bus oriented applica-
tions. The device is byte controlled. The flip-flops appear
transparent to the data when the Latch Enable (LE) is HIGH.
When LE is low, the data that meets the setup time is
latched. Data appears on the bus when the Output Enable
(OE) is LOW. When OE is HIGH, the outputs are in high Z
state.
Ordering Code:
Logic Symbol
Pin Description
TRI-STATE
54ABT16373W-QML
OE
LE
D
O
Pin Names
0
0
–D
n
–O
n
15
15
®
is a registered trademark of National Semiconductor Corporation.
Military
Output Enable Input (Active Low)
Latch Enable Input
Data Inputs
Outputs
Description
DS100201
WA48A
Package
Number
48-Lead Cerpack
DS100201-1
Features
n Separate control logic for each byte
n 16-bit version of the ABT373
n High impedance glitch free bus loading during entire
n Non-destructive hot insertion capability
n Guaranteed latch-up protection
n Standard Microcircuit Drawing (SMD) 5962-9320001
Connection Diagram
power up and power down cycle
Package Description
Pin Assignment for Cerpack
®
Outputs
DS100201-2
www.national.com
July 1998

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54ABT16373W-QML Summary of contents

Page 1

... When LE is low, the data that meets the setup time is latched. Data appears on the bus when the Output Enable (OE) is LOW. When OE is HIGH, the outputs are in high Z state. Ordering Code: Military Package Number 54ABT16373W-QML WA48A Logic Symbol Pin Description Pin Names Description OE Output Enable Input (Active Low) ...

Page 2

Functional Description The ABT16373 contains sixteen D-type latches with TRI-STATE standard outputs. The device is byte controlled with each byte functioning identically, but independent of the other. Control pins can be shorted together to obtain full 16-bit operation. The following ...

Page 3

Absolute Maximum Ratings Storage Temperature Ambient Temperature under Bias Junction Temperature under Bias Ceramic V Pin Potential to CC Ground Pin Input Voltage (Note 2) Input Current (Note 2) Voltage Applied to Any Output in the Disabled or Power-Off State ...

Page 4

AC Electrical Characteristics Symbol Parameter t Propagation Delay PLH PHL Propagation Delay PLH PHL n t Output Enable Time PZH t PZL t Output Disable Time PHZ t PLZ ...

Page 5

AC Loading DS100201-6 * Includes jig and probe capacitance FIGURE 1. Standard AC Test Load FIGURE 2. Test Input Signal Levels Amplitude Rep. Rate 3.0V 1 MHz 500 ns 2.5 ns FIGURE 3. Test Input Signal Requirements ...

Page 6

... National Semiconductor Asia Pacific Customer Fax: +49 (0) 1 80-530 85 86 Response Group Email: europe.support@nsc.com Tel: 65-2544466 Fax: 65-2504466 Tel: +49 (0) 1 80-532 78 32 Email: sea.support@nsc.com Tel: +49 (0) 1 80-534 16 80 National Semiconductor Japan Ltd. Tel: 81-3-5620-6175 Fax: 81-3-5620-6179 ...

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