FAGD1652248BA Intel, FAGD1652248BA Datasheet - Page 2

• Manufacturer Part Number: FAGD1652248BA
• Manufacturer: Intel

Specifications of FAGD1652248BA

• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Pin Count: 48
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

Functional Details
The main application of the GD16522 is
as a receiver for optical communication
systems:
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The GD16522 integrates:
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into a Phase Locked Loop (PLL) - based
multi-rate clock and data recovery circuit
with differential CML data and clock
outputs.
VCO
The VCO is a low noise LC-type differen-
tial oscillator with a tuning range from 2.4
to 2.6 GHz. Tuning is done by applying a
voltage to the VCTL pin.
Lock Detect Circuit
The internal lock detect circuit continu-
ously monitors the difference between
the reference clock and the divided VCO
clock. If the reference clock and the di-
vided VCO frequency differ by more than
500 ppm, it switches the PFD into the
PLL in order to pull the VCO back inside
the lock-in range. This mode is called the
acquisition mode.
The PFD is used to ensure predictable
lock up conditions for the GD16522 by
locking the VCO to an external reference
clock source. It is only used during acqui-
sition and pulls the VCO into the lock-in
range where the Bang-Bang phase de-
tector is capable of acquiring lock. The
PFD is made with digital set/reset cells
giving it a true phase and frequency
characteristic.
Once the VCO is inside the lock-range
the lock-detection circuit switches the
Bang-Bang phase detector into the PLL
in order to lock to the data signal. This
mode is called CDR mode.
If the divided VCO frequency differs from
the reference frequency by ±500 ppm,
i.e. due to data loss, the internal lock de-
tect circuit will give a stable output clock
during a loss of data condition.
The reference clock to the PFD is at 1/64
of the STM16 / OC-48 data rate. By
Data Sheet Rev.: 21
SDH STM-16 / 4 / 1
SONET OC-48 / 12 / 3
Gigabit Ethernet
a Limiting Amplifier
a Digital LOS Alarm
a Continuous Bit Detector
Serial loop-back input
a Voltage Controlled Oscillator (VCO)
a Lock Detect Circuit
a Frequency Detector (PFD)
a Bang-Bang Phase Detector
using REF_SEL pin the reference clock
input (RCIP/N) can be chosen to use a
155.52 MHz or 38.88 MHz differential
PECL reference clock. The reference
clock frequency is independent of the
chosen data rate.
The BC_DET Signal
An internal circuit monitors input data
transitions and gives a BC_DET output
signal which is asserted if more than 256
consecutive identical bits, 0s or 1s, are
detected.
BC_DET will be de-asserted only after
approximately 16 bit transitions are de-
tected within a time period proportional to
the selected data rate (50 ns at STM 16 /
OC-48).
Bang-Bang Phase Detector
The Bang-Bang phase detector is used
in CDR mode as a true digital type de-
tector, producing a binary output. It sam-
ples the incoming data twice each bit
period: once in the transition of the (pre-
vious) bit period and once in the middle
of the bit period. When a transition oc-
curs between 2 consecutive bits - the
value of the sample in the transition be-
tween the bits will show whether the
VCO clock leads or lags the data. Hence
the PLL is controlled by the bit transition
point, thereby ensuring that data is sam-
pled in the middle of the eye, once the
system is in CDR mode. The external
loop filter components control the charac-
teristics of the PLL.
The binary output of either the PFD or
the Bang-Bang phase detector (depend-
ing of the mode of the lock-detection cir-
cuit) is passed to a charge pump which
can sink or source current or tristate. The
output of the charge pump is filtered by
the external loop filter and controls the
tuning voltage of the VCO.
As a result of the continuous monitoring
of the lock-detect circuit, the VCO fre-
quency never deviates more than
500 ppm from the reference clock before
the PLL is considered to be ’Out of Lock’.
Hence the acquisition time is predictable
and short and the output clock (SCOP/N)
is always kept within the 500 ppm limits,
ensuring safe clocking of downstream
circuitry.
GD16522
The LOCK_DET Signal
The LOCK_DET signal is a status output,
which monitors the status of the internal
lock detect circuit of the GD16522 CDR
logic and the output of the BC_DET cir-
cuit.
LOCK_DET is asserted (set HIGH) if the
VCO frequency differs from the reference
frequency by ±500 ppm. This ‘ out of
lock’ condition is detected by the internal
Lock Detect circuit described previously.
LOCK_DET is also asserted in the case
of the absence of data, which is detected
by the BC_DET circuit within the reaction
time of the internal PLL lock detect
system.
If data is absent, the divided VCO fre-
quency will drift away from the reference
frequency until they differ by ±500 ppm.
The internal Lock Detect logic will alter-
nate between CDR and acquisition mode
until data returns, enabling the GD16522
to acquire lock and function in CDR
mode.
The LOCK_DET signal, however, will re-
main asserted until BC_DET is de- as-
serted and the internal lock detect circuit
is operating in CDR mode.
The CDR circuitry of the GD16522 has
been fine-tuned to provide an accurate
stable clock output from the VCO when
data is present. Due to the precise nature
of the internal VCO, when data is absent
the clock output frequency will drift slowly
from the recovered clock frequency until
an out of lock condition is detected. The
time taken for the GD16522 to go ‘out of
lock’ in the absence of data will typically
be at least 3 ms, unless an external cir-
cuit is used to pull the VCO frequency
away from the reference frequency.
When loss of data is detected, i.e.
BC_DET is asserted, or the divided VCO
frequency differs from the reference fre-
quency by ±500 ppm, LOCK_DET is as-
serted and the internal lock detect circuit
switches to acquisition mode. This will
give a stable output clock during a loss of
data condition.
When BC_DET is de-asserted and the
divided VCO frequency is within 500 ppm
of the reference frequency, LOCK_DET
will be de-asserted within 500 ms, inde-
pendent of selected data rate.
A bonding option is available which en-
ables the LOCK_DET output to monitor
the status of the LOS_DET circuit in ad-
dition to the internal lock and BC_DET.
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