82V3001APV IDT, Integrated Device Technology Inc, 82V3001APV Datasheet - Page 11

• Manufacturer Part Number: 82V3001APV
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of 82V3001APV

• Function: Wan PLL
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Package Type: SSOP
• Pin Count: 56
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

3.1.1
synchronized to the network is required.
C4o, C6o, C8o, C16o and C32o) and synchronization (F0o, F8o, F16o,
F32o, TSP, RSP) signals, which are synchronous to the input reference.
The input reference signal has a nominal frequency of 8 kHz, 2.048 MHz
or 1.544 MHz.
most to make the output signals synchronous (phase locked) to the input
reference.
indication by setting the NORMAL pin to high.
3.1.2
IDT82V3001A to lock to a reference more quickly than Normal Mode will
do. Typically, the DPLL will lock to the input reference within 500 ms if
the FLOCK pin is high.
FUNCTIONAL DESCRIPTION
IDT82V3001A
Normal Mode is typically used when a slave clock source
In this mode, the IDT82V3001A provides timing (C1.5o, C3o, C2o,
From a reset condition, the IDT82V3001A will take 30 seconds at
Whenever the IDT82V3001A enters Normal Mode, it will give an
Fast Lock Mode is a submode of Normal Mode. It is used to allow the
NORMAL MODE
FAST LOCK MODE
* Note: After reset, Mode_sel1 and Mode_sel0 should be initially set to '10' or '00'.
Mode_sel1=0
Mode_sel0=0
Normal
S1
Figure - 4 State Control Diagram
(Valid Input Reference Signal)
(Invalid Input Reference Signal)
(Valid Input Reference Signal)
TIE Enable (TIE_en = H)
TIE Disable (TIE_en = L)
Auto TIE Disable
Mode_sel1=1
Mode_sel0=0
Mode_sel1=0
Mode_sel0=1
Holdover
Freerun
Reset *
S0
S3
11
3.1.3
while network synchronization is temporarily disrupted.
synchronization signals, which are not locked to the external reference
signal but based on storage techniques. The storage value is
determined while the device is in Normal Mode and locked to the
external reference signal.
reference signal, a numerical value corresponding to the output
frequency is stored alternately in two memory locations every 30 ms.
When the device is switched into Holdover Mode, the stored value in
memory from between 30 ms and 60 ms is used to set the output
frequency of the device.
corresponds to the worst case of 18 frame (125 µs per frame) slips in 24
hours. This meets AT&T TR62411 requirement of ±0.37 ppm (255 frame
slips per 24 hours).
IDT82V3001A goes into Holdover Mode.
Holdover Mode is typically used for short duration (e.g., 2 seconds)
In Holdover Mode, the IDT82V3001A provides timing and
In Normal Mode, when the output signal is locked to the input
The frequency accuracy in Holdover Mode is ±0.025 ppm, which
The HOLDOVER pin will be set to logic high whenever the
HOLDOVER MODE
WAN PLL WITH SINGLE REFERENCE INPUT
Auto - Holdover
Mode_sel1=0
Mode_sel0=0
S2
October 15, 2008