DM74ALS521WMXNL Fairchild Semiconductor, DM74ALS521WMXNL Datasheet
DM74ALS521WMXNL
Manufacturer Part Number
DM74ALS521WMXNL
Description
Manufacturer
Fairchild Semiconductor
Type
Identity Comparatorr
Datasheet
1.DM74ALS521WMXNL.pdf
(5 pages)
Specifications of DM74ALS521WMXNL
Logic Family
ALS
Technology
Bipolar
High Level Output Current
-2.6mA
Low Level Output Current
24mA
Output Function
A=B
Package Type
SOIC
Mounting
Surface Mount
Pin Count
20
Polarity
Inverting
Abs. Propagation Delay Time
22ns
Operating Supply Voltage (typ)
5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
4.5V
Operating Temperature (max)
70C
Operating Temperature (min)
0C
Operating Temperature Classification
Commercial
Number Of Bits
8
Lead Free Status / RoHS Status
Compliant
© 2000 Fairchild Semiconductor Corporation
DM74ALS520WM
DM74ALS520N
DM74ALS521WM
SM74ALS521N
DM74ALS520 • DM74ALS521
8-Bit Comparator
General Description
These comparators perform an “equal to” comparison of
two 8-bit words with provision for expansion or external
enabling. The matching of the two 8-bit input plus a logic
LOW on the EN input produces the output A
DM74ALS520 and DM74ALS521. The DM74ALS520 and
DM74ALS521 have totem pole outputs for wire AND cas-
cading. Additionally, the DM74ALS520 is provided with B
input pull up termination resistors for analog or switch data.
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Ordering Code
Package Number
M20B
M20B
N20A
N20A
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
DS006114
B on the
Features
Function Table
H
L
X
Switching specifications at 50 pF
Switching specifications guaranteed over full tempera-
ture and V
Advanced oxide-isolated, ion-implanted Schottky TTL
process
Functionally and pin for pin compatible with LS family
counterpart
Improved output transient handling capability
LOW Logic Level
Don't Care
HIGH Logic Level
Package Description
EN
CC
H
L
L
range
Inputs
A
A
Data
X
September 1986
Revised April 2000
B
B
www.fairchildsemi.com
Output
A
H
H
L
B
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DM74ALS521WMXNL Summary of contents
Page 1
... Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram © 2000 Fairchild Semiconductor Corporation Features Switching specifications Switching specifications guaranteed over full tempera- ...
Page 2
Logic Diagram www.fairchildsemi.com 2 ...
Page 3
Absolute Maximum Ratings Supply Voltage Input Voltage Operating Free Air Temperature Range Storage Temperature Range Typical JA N Package M Package Recommended Operating Conditions Symbol Parameter V Supply Voltage CC V HIGH Level Input Voltage IH V LOW Level Input ...
Page 4
Physical Dimensions inches (millimeters) unless otherwise noted 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide www.fairchildsemi.com Package Number M20B 4 ...
Page 5
Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right ...