74SSTUA32866BFG8 IDT, Integrated Device Technology Inc, 74SSTUA32866BFG8 Datasheet - Page 10

• Manufacturer Part Number: 74SSTUA32866BFG8
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of 74SSTUA32866BFG8

• Logic Family: SSTU
• Logical Function: Registered Buffer
• Number Of Elements: 1
• Number Of Bits: 25
• Number Of Inputs: 25
• Number Of Outputs: 25
• High Level Output Current: -8mA
• Low Level Output Current: 8mA
• Propagation Delay Time: 2.4ns
• Operating Supply Voltage (typ): 1.8V
• Operating Supply Voltage (max): 1.9V
• Operating Supply Voltage (min): 1.7V
• Clock-edge Trigger Type: Posit/Negat-Edge
• Polarity: Non-Inverting
• Technology: CMOS
• Frequency (max): 410(Min)MHz
• Mounting: Surface Mount
• Pin Count: 96
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Compliant

TERMINAL FUNCTIONS (ALL PINS)
ABSOLUTE MAXIMUM RATINGS
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
2. The input and output negative voltage ratings may be exceeded if the ratings of the
3. This value is limited to 2.5V maximum.
IDT74SSTUA32866
1.8V CONFIGURABLE REGISTERED BUFFER WITH ADDRESS-PARITY TEST
Symbol
V
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
I/P and O/P clamp current are observed.
V
T
CSR, DCS
V
V
O
I
Terminal
I
I
I
STG
OK
QCKEx
PAR_IN
(2,3)
DD
IK
DD
RESET
QODTx
O
(2,3)
DCKE
QCSx
QERR
DODT
Name
GND
PPO
V
CLK
CLK
V
C x
Q x
Dx
REF
DD
Description
Supply Voltage Range
Input Voltage Range
Output Voltage Range
Input Clamp Current
Output Clamp Current V
Continuous Output Current,
V
Continuous Current through each
V
Storage Temperature Range
O
DD
= 0 to V
or GND
Open Drain Output
Characteristics
LVCMOS Input
LVCMOS Input
Differential Input
Differential Input
SSTL_18 Input
SSTL_18 Input
SSTL_18 Input
SSTL_18 Input
SSTL_18 Input
1.8V nominal
0.9V nominal
1.8V CMOS
1.8V CMOS
1.8V CMOS
1.8V CMOS
1.8V CMOS
Ground Input
Electrical
DD
V
V
V
I
I
O
O
< 0
> V
< 0
> V
Asynchronous Reset Input. Resets registers and disables V
DD
Description
Ground
Power Supply Voltage
Input Reference Voltage
Positive Master Clock Input
Negative Master Clock Input
Configuration Control Inputs
Chip Select Inputs. Disables outputs Dx switching when both inputs are HIGH.
Data Input. Clocked in on the crossing of the rising edge of CLK and the falling edge of CLK.
The outputs of this register bit will not be suspended by the DCS and CSR controls
The outputs of this register bit will not be suspended by the DCS and CSR controls
Data Outputs that are suspended by the DCS and CSR controls
Data Output that will not be suspended by the DCS and CSR controls
Data Output that will not be suspended by the DCS and CSR controls
Data Output that will not be suspended by the DCS and CSR controls
Parity Input. Clocked on the rising edge of CLK one cycle after corresponding data input.
Output Error bit, generated one cycle after the corresponding data output
Partial Parity Output. Indicates ODD parity of Data Inputs and Parity In.
DD
–0.5 to V
–65 to +150
–0.5 to 2.5
–0.5 to 2.5
Max.
±100
±50
±50
±50
DD
+0.5
(1)
Unit
mA
mA
mA
mA
°C
V
V
V
10
MODE SELECT
C
0
0
1
1
0
C
0
1
0
1
1
REF
data and clock differential-input receivers.
1:1 25-bit to 25-bit
1:2 14-bit to 28-bit, Front (Type A)
Reserved
1:2 14-bit to 28-bit, Back (Type B)
COMMERCIAL TEMPERATURE RANGE
Device Mode