74HCT7030D-T NXP Semiconductors, 74HCT7030D-T Datasheet - Page 18
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74HCT7030D-T
Manufacturer Part Number
74HCT7030D-T
Description
Manufacturer
NXP Semiconductors
Datasheet
1.74HCT7030D-T.pdf
(22 pages)
Specifications of 74HCT7030D-T
Logic Family
HCT
Logical Function
FIFO Register
Number Of Elements
1
Number Of Bits
9
Number Of Inputs
9
Number Of Outputs
9
High Level Output Current
-6mA
Low Level Output Current
6mA
Package Type
SO
Propagation Delay Time
117ns
Operating Supply Voltage (typ)
5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
4.5V
Polarity
Non-Inverting
Technology
CMOS
Frequency (max)
36(Typ)MHz
Mounting
Surface Mount
Pin Count
28
Operating Temp Range
-40C to 125C
Operating Temperature Classification
Automotive
Quiescent Current
50uA
Output Type
3-State
Lead Free Status / RoHS Status
Compliant
Philips Semiconductors
Expanded format
Fig.19 shows two cascaded FIFOs providing a capacity of 128 words
Fig.20 shows the signals on the nodes of both FIFOs after the application of a SI pulse, when both FIFOs are initially
empty. After a rippled through delay, data arrives at the output of FIFO
generated. The requirements of SI
edge of DOR
Fig.21 shows the signals on the nodes of both FIFOs after the application of a SO
full. After a bubble-up delay a DIR
from the output of FIFO
width of DOR
Fig.22 shows the waveforms at all external nodes of both FIFOs during a complete shift-in and shift-out sequence.
December 1990
9-bit x 64-word FIFO register; 3-state
The PC74HC/HCT7030 is easily cascaded to increase word capacity without any
external circuitry. In cascaded format, all necessary communications are handled
by the FIFOs. Figs 17 to 19 demonstrate the intercommunication timing between
FIFO
FIFOs, when shifted full and shifted empty again.
A
and FIFO
A
B
. After a second bubble-up delay an empty space arrives at D
and Q
B
. Fig.22 gives an overview of pulses and timing of two cascaded
nA
. After a second ripple through delay, data arrives at the output of FIFO
A
to the input of FIFO
Fig.19 Cascading for increased word capacity; 128 words
B
B
pulse is generated, which acts as a SO
and D
nB
B
are satisfied by the DOR
. The requirements of the SO
18
A
A
pulse width and the timing between the rising
9 bits.
. Due to SO
A
A
nA
pulse for FIFO
pulse for FIFO
, at which time DIR
B
pulse, when both FIFOs are initially
A
being HIGH, a DOR pulse is
9 bits.
A
A
74HC/HCT7030
. One word is transferred
is satisfied by the pulse
B
.
A
Product specification
goes HIGH.