A2550KLP-T Allegro Microsystems Inc, A2550KLP-T Datasheet - Page 10

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A2550KLP-T

Manufacturer Part Number
A2550KLP-T
Description
Manufacturer
Allegro Microsystems Inc
Datasheet

Specifications of A2550KLP-T

Lead Free Status / RoHS Status
Compliant
A2550
VREG5 UVLO
Timing Diagram: VREG5 UVLO and TSD Monitoring
VREG5
Internal
Internal
1.
2.
3.
4.
5.
CPOR
NPOR
OUTx
CWD
VBB
TSD
WDI
VREG5 undervoltage detected.
VREG5 recovers, and after it rises above V
UVLO flag is deactivated and CPOR recharges.
NPOR inactive, but outputs not enabled until watchdog detected.
TSD event detected and NPOR is activated. When V
VREG5 shuts down.
TSD flag deactivated (VREG5 allowed to rise; steps 2 and 3 repeat)
outputs enabled
1
2
3
~INx
Relay Driver with 5 V Regulator
4
Internal V
Internal V
V
for Automotive Applications
UVREG5
UVREG5
ref
ref
5
+ V
REG5
UVREG5(Hys)
≤ V
115 Northeast Cutoff
1.508.853.5000; www.allegromicro.com
Allegro MicroSystems, Inc.
Worcester, Massachusetts 01615-0036 U.S.A.
UVREG5
~INx
,
,
10

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