EVAL-AD7273CB Analog Devices Inc, EVAL-AD7273CB Datasheet - Page 15

• Manufacturer Part Number: EVAL-AD7273CB
• Manufacturer: Analog Devices Inc

Specifications of EVAL-AD7273CB

• Lead Free Status / RoHS Status: Not Compliant

CIRCUIT INFORMATION
The AD7273/AD7274 are high speed, low power, 10-/12-bit,
single supply ADCs, respectively. The parts can be operated
from a 2.35 V to 3.6 V supply. When operated from any supply
voltage within this range, the AD7273/AD7274 are capable of
throughput rates of 3 MSPS when provided with a 48 MHz clock.
The AD7273/AD7274 provide the user with an on-chip track-
and-hold ADC and a serial interface housed in an 8-lead TSOT
or an 8-lead MSOP package, which offers the user considerable
space-saving advantages over alternative solutions. The serial
clock input accesses data from the part and provides the clock
source for the successive approximation ADC. The analog input
range is 0 to V
V
The AD7273/AD7274 also feature a power-down option to save
power between conversions. The power-down feature is
implemented across the standard serial interface as described in
the Modes of Operation section.
CONVERTER OPERATION
The AD7273/AD7274 are successive approximation ADCs
based on a charge redistribution DAC. Figure 24 and Figure 25
show simplified schematics of the ADC. Figure 24 shows the
ADC during its acquisition phase, where SW2 is closed, SW1 is
in Position A, the comparator is held in a balanced condition,
and the sampling capacitor acquires the signal on V
DD
V
is required by the ADC.
IN
SW1
A
REF
B
AGND
. An external reference in the range of 1.4 V to
CAPACITOR
SAMPLING
Figure 24. ADC Acquisition Phase
ACQUISITION
PHASE
V
DD
/2
SW2
COMPARATOR
REDISTRIBUTION
CHARGE
CONTROL
DAC
LOGIC
IN
.
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When the ADC starts a conversion, SW2 opens and SW1 moves
to Position B, causing the comparator to become unbalanced
(see Figure 25). The control logic and the charge redistribution
DAC are used to add and subtract fixed amounts of charge from
the sampling capacitor to bring the comparator back into a
balanced condition. When the comparator is rebalanced, the
conversion is complete. The control logic generates the ADC
output code. Figure 26 shows the ADC transfer function.
ADC TRANSFER FUNCTION
The output coding of the AD7273/AD7274 is straight binary.
The designed code transitions occur midway between
successive integer LSB values, such as 0.5 LSB and 1.5 LSB. The
LSB size is V
AD7273. The ideal transfer characteristic for the
AD7273/AD7274 is shown in Figure 26.
V
IN
SW1
Figure 26. AD7273/AD7274 Transfer Characteristic
111...111
111...110
111...000
011...111
000...010
000...001
000...000
A
REF
AGND
B
/4,096 for the AD7274 and V
CAPACITOR
SAMPLING
Figure 25. ADC Conversion Phase
ACQUISITION
0V
PHASE
0.5LSB
V
DD
/2
ANALOG INPUT
SW2
1LSB = V
1LSB = V
COMPARATOR
REF
REF
AD7273/AD7274
+V
/4096 (AD7274)
/1024 (AD7273)
REF
REDISTRIBUTION
REF
– 1.5LSB
CHARGE
/1,024 for the
CONTROL
DAC
LOGIC