AD5255BRU250-RL7 Analog Devices Inc, AD5255BRU250-RL7 Datasheet - Page 4

• Manufacturer Part Number: AD5255BRU250-RL7
• Manufacturer: Analog Devices Inc

Specifications of AD5255BRU250-RL7

• Number Of Elements: 3
• Resistance (max): 250KOhm
• Power Supply Requirement: Single/Dual
• Interface Type: Serial (2-Wire/I2C)
• Single Supply Voltage (typ): 5V
• Dual Supply Voltage (typ): ±2.5V
• Single Supply Voltage (min): 2.7V
• Single Supply Voltage (max): 5.5V
• Dual Supply Voltage (min): ±2.2V
• Dual Supply Voltage (max): ±2.7V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 24
• Lead Free Status / RoHS Status: Not Compliant

AD5255
Parameter
DIGITAL INPUTS AND OUTPUTS
POWER SUPPLIES
1
2
3
4
5
6
7
Typical represents average readings at 25°C, V
Resistor position nonlinearity error, R-INL, is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
INL and DNL are measured at V
Resistor Terminals A, B, W have no limitations on polarity with respect to each other.
Guaranteed by design and not subject to production test.
Bandwidth, noise, and settling time are dependent on the terminal resistance value chosen. The lowest R value results in the fastest settling time and highest
P
positions. R-DNL measures the relative step change from ideal between successive tap positions.
bandwidth. The highest R value results in the minimum overall power consumption.
DISS
Input Logic High
Input Logic Low
Output Logic High (SDA)
Output Logic Low
WP Leakage Current
A0 Leakage Current
Input Leakage Current (Excluding WPand A0)
Input Capacitance
Single-Supply Power Range
Dual-Supply Power Range
Positive Supply Current
Negative Supply Current
EEMEM Data Storing Mode Current
EEMEM Data Restoring Mode Current
Power Dissipation
Power Supply Sensitivity
is calculated from (I
SDA
SCL
P
5
7
DD
t
× V
1
DD
S
W
5
). CMOS logic level inputs result in minimum power dissipation.
with the RDAC configured as a potentiometer divider similar to a voltage output DAC. V
t
2
DD
t
3
= 5 V.
t
8
t
8
Symbol
V
V
V
V
I
I
I
C
V
V
I
I
I
I
P
P
t
WP
A0
I
DD
SS
DD_STORE
DD_RESTORE
9
IH
IL
OH
OL
DD
DD
DISS
SS
I
/V
SS
t
Figure 2. I
6
Rev. A | Page 4 of 20
t
t
4
9
2
C Timing Diagram
Conditions
V
V
V
V
V
V
R
V
R
V
WP = V
A0 = GND
V
V
V
V
V
V
V
V
∆V
DD
DD
DD
DD
DD
DD
PULL-UP
SS
PULL-UP
SS
IN
SS
IH
IH
DD
IH
IH
IH
DD
t
= 0 V or V
= V
= V
= V
= V
= V
/V
/V
/V
/V
= 0 V
= 0 V
= 0 V
7
= 5 V, V
= 5 V, V
= 2.5 V, V
= 5 V ± 10%
SS
SS
SS
SS
DD
DD
DD
DD
DD
= 2.2 kΩ to V
= 2.2 kΩ to V
DD
= +2.7 V/0 V or
= ±2.5 V
= +2.7 V/0 V or
= ±2.5 V
or V
or V
or V
or V
= 5 V or V
SS
SS
DD
IL
IL
SS
IL
IL
= 0 V
= 0 V
S
= GND, V
= GND,
= GND
= GND
= −2.5 V
t
5
IL
DD
DD
= GND
= 5 V,
= 5 V,
SS
t
= 0 V
2
A
= V
DD
Min
2.4
2.1
4.9
2.7
±2.2
5
and V
B
= 0 V.
Typ
5
5
−5
35
2.5
25
0.01
1
Max
0.8
0.6
0.4
9
3
±1
5.5
±2.7
5
15
−15
75
0.025
P
t
10
Unit
V
V
V
V
V
V
μA
μA
μA
pF
V
V
μA
μA
mA
mA
μW
%/%