ADM1070ARTZ Analog Devices Inc, ADM1070ARTZ Datasheet - Page 4

• Manufacturer Part Number: ADM1070ARTZ
• Manufacturer: Analog Devices Inc

Specifications of ADM1070ARTZ

• Linear Misc Type: Negative Voltage
• Family Name: ADM1070
• Package Type: SOT-23
• Operating Supply Voltage (min): -18V
• Operating Supply Voltage (max): -80V
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Industrial
• Product Depth (mm): 1.6mm
• Product Height (mm): 1.15mm
• Product Length (mm): 2.9mm
• Mounting: Surface Mount
• Pin Count: 6
• Lead Free Status / RoHS Status: Compliant

ADM1070
Pin No.
1
2
3
4
5
6
Mnemonic
SENSE
V
V
TIMER
UV/OV
GATE
EE
IN
Function
Connection to External FET Source Voltage. A sense resistor is connected in the supply path
between the SENSE Pin and V
faults. This voltage is fed as an input to the linear current regulator. When it reaches 100 mV for
a specified period, t
device. If current monitoring is not required, this feature can be turned off by shorting the
SENSE Pin and V
Device Negative Supply Voltage. This pin should be connected to the lower potential of the
power supply.
Shunt Regulated On-Chip Supply, Nominally V
through a dropper resistor that is connected to the higher potential of the power supply inputs.
Allows User Control over Timing Functions by Determining Frequency of Oscillator. Fre-
quency set by connecting external capacitor to V
default to internally set value.
Input Pin for Overvoltage and Undervoltage Detection Circuitry. The voltage appearing on the
UV/OV Pin is proportional to board supply and is determined by external resistors. When the
voltage on UV/OV falls below the undervoltage threshold of 0.86 V, the GATE Pin is driven low.
When the voltage appearing at the UV/OV Pin rises above the overvoltage threshold of 1.97 V,
the GATE Pin is also driven low. If the external resistor ratio of R1/R2 = 40 is used, then this
gives an operating range of –36 V to –77 V.
Output to External FET Gate Drive. Controlled by linear current regulator. The gate is driven
low if an overvoltage or undervoltage fault occurs or if a current fault lasts for longer than the
time, t
No external compensation is required. When the FET is fully enhanced and the load capacitance
has been charged, the GATE Pin reaches a high level of typically 12 V.
ON
. When in linear regulation, the GATE Pin voltage is controlled as part of the servo loop.
PIN FUNCTION DESCRIPTION
SENSE
PIN CONFIGURATION
V
EE
EE
V
ON
IN
together.
, the regulator reduces the gate voltage and drives the FET as a linear pass
1
2
3
ADM1070ART
(Not to Scale)
TOP VIEW
–4–
EE
, and the voltage across this resistor is monitored to detect current
6
5
4
GATE
UV/OV
TIMER
EE
EE
. Tying pin directly to V
+ 12.3 V. This pin should be current fed
EE
causes oscillator to
REV. 0