MT47H128M8HQ-25:G Micron Technology Inc, MT47H128M8HQ-25:G Datasheet - Page 8
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MT47H128M8HQ-25:G
Manufacturer Part Number
MT47H128M8HQ-25:G
Description
Manufacturer
Micron Technology Inc
Type
DDR2 SDRAMr
Datasheet
1.MT47H128M8HQ-25G.pdf
(134 pages)
Specifications of MT47H128M8HQ-25:G
Organization
128Mx8
Density
1Gb
Address Bus
17b
Access Time (max)
400ps
Maximum Clock Rate
800MHz
Operating Supply Voltage (typ)
1.8V
Package Type
FBGA
Operating Temp Range
0C to 85C
Operating Supply Voltage (max)
1.9V
Operating Supply Voltage (min)
1.7V
Supply Current
160mA
Pin Count
60
Mounting
Surface Mount
Operating Temperature Classification
Commercial
Lead Free Status / RoHS Status
Compliant
1Gb: x4, x8, x16 DDR2 SDRAM
Figure 51: READ-to-PRECHARGE – BL = 8 ...................................................................................................... 98
Figure 52: Bank Read – Without Auto Precharge ............................................................................................ 100
Figure 53: Bank Read – with Auto Precharge .................................................................................................. 101
t
t
Figure 54: x4, x8 Data Output Timing –
DQSQ,
QH, and Data Valid Window ................................................. 102
t
t
Figure 55: x16 Data Output Timing –
DQSQ,
QH, and Data Valid Window ..................................................... 103
t
t
Figure 56: Data Output Timing –
AC and
DQSCK ......................................................................................... 104
Figure 57: Write Burst ................................................................................................................................... 106
Figure 58: Consecutive WRITE-to-WRITE ...................................................................................................... 107
Figure 59: Nonconsecutive WRITE-to-WRITE ................................................................................................ 107
Figure 60: WRITE Interrupted by WRITE ....................................................................................................... 108
Figure 61: WRITE-to-READ ........................................................................................................................... 109
Figure 62: WRITE-to-PRECHARGE ................................................................................................................ 110
Figure 63: Bank Write – Without Auto Precharge ............................................................................................ 111
Figure 64: Bank Write – with Auto Precharge ................................................................................................. 112
Figure 65: WRITE – DM Operation ................................................................................................................ 113
Figure 66: Data Input Timing ........................................................................................................................ 114
Figure 67: Refresh Mode ............................................................................................................................... 115
Figure 68: Self Refresh .................................................................................................................................. 117
Figure 69: Power-Down ................................................................................................................................ 119
Figure 70: READ-to-Power-Down or Self Refresh Entry .................................................................................. 121
Figure 71: READ with Auto Precharge-to-Power-Down or Self Refresh Entry .................................................. 121
Figure 72: WRITE-to-Power-Down or Self Refresh Entry ................................................................................ 122
Figure 73: WRITE with Auto Precharge-to-Power-Down or Self Refresh Entry ................................................. 122
Figure 74: REFRESH Command-to-Power-Down Entry ................................................................................. 123
Figure 75: ACTIVATE Command-to-Power-Down Entry ................................................................................ 123
Figure 76: PRECHARGE Command-to-Power-Down Entry ............................................................................ 124
Figure 77: LOAD MODE Command-to-Power-Down Entry ............................................................................ 124
Figure 78: Input Clock Frequency Change During Precharge Power-Down Mode ........................................... 125
Figure 79: RESET Function ........................................................................................................................... 127
Figure 80: ODT Timing for Entering and Exiting Power-Down Mode .............................................................. 129
Figure 81: Timing for MRS Command to ODT Update Delay .......................................................................... 130
Figure 82: ODT Timing for Active or Fast-Exit Power-Down Mode ................................................................. 130
Figure 83: ODT Timing for Slow-Exit or Precharge Power-Down Modes ......................................................... 131
Figure 84: ODT Turn-Off Timings When Entering Power-Down Mode ............................................................ 131
Figure 85: ODT Turn-On Timing When Entering Power-Down Mode ............................................................. 132
Figure 86: ODT Turn-Off Timing When Exiting Power-Down Mode ............................................................... 133
Figure 87: ODT Turn-On Timing When Exiting Power-Down Mode ................................................................ 134
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1GbDDR2.pdf – Rev. V 6/10 EN
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