K4S641632N-LI60000 Samsung Semiconductor, K4S641632N-LI60000 Datasheet - Page 4

• Manufacturer Part Number: K4S641632N-LI60000
• Manufacturer: Samsung Semiconductor
• Type: SDRAMr

Specifications of K4S641632N-LI60000

• Organization: 4Mx16
• Density: 64Mb
• Address Bus: 14b
• Access Time (max): 6/5ns
• Maximum Clock Rate: 166MHz
• Operating Supply Voltage (typ): 3.3V
• Package Type: TSOP-II
• Operating Temp Range: -40C to 85C
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Supply Current: 120mA
• Pin Count: 54
• Mounting: Surface Mount
• Operating Temperature Classification: Industrial
• Lead Free Status / RoHS Status: Compliant

1M x 16Bit x 4Banks SDRAM
1.0 FEATURES
• JEDEC standard 3.3V power supply
• LVTTL compatible with multiplexed address
• Four banks operation
• MRS cycle with address key programs
• All inputs are sampled at the positive going edge of the system clock
• Burst read single-bit write operation
• DQM (x8) & L(U)DQM (x16) for masking
• Auto & self refresh
• 64ms refresh period (4K cycle)
• Pb-free and Halogen-free Package
• RoHS compliant
• Support Industrial Temp (-40 to 85°C)
2.0 GENERAL DESCRIPTION
with SAMSUNG′s high performance CMOS technology. Synchronous design allows precise cycle control with the use of system clock I/
O transactions are possible on every clock cycle. Range of operating frequencies, programmable burst length and programmable laten-
cies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications.
3.0 Ordering Information
K4S641632N
The K4S641632N is 67,108,864 bits synchronous high data rate Dynamic RAM organized as 4 x 1,048,576 words by 16 bits, fabricated
-. CAS latency (2 & 3)
-. Burst length (1, 2, 4, 8 & Full page)
-. Burst type (Sequential & Interleave)
K4S641632N-LI/P60
K4S641632N-LI/P75
Part No.
Organization
4Mx16
Orgainization
Row & Column address configuration
4Mb x 16
Row Address
A0~A11
4 of 14
166MHz(CL=3)
133MHz(CL=3)
Max Freq.
Industrial
Column Address
A0-A7
Interface
LVTTL
Synchronous DRAM
Rev. 1.1 December 2007
Pb-Free & Halogen-Free
54pin TSOP(II)
Package