WS57C256F-70J STMicroelectronics, WS57C256F-70J Datasheet

WS57C256F-70J

Manufacturer Part Number

WS57C256F-70J

Description

Manufacturer

STMicroelectronics

Datasheet

1.WS57C256F-70J.pdf (5 pages)

Specifications of WS57C256F-70J

Organization

32Kx8

Interface Type

Parallel

In System Programmable

In System/External

Access Time (max)

70ns

Reprogramming Technique

Operating Supply Voltage (typ)

Operating Supply Voltage (min)

4.5V

Operating Supply Voltage (max)

5.5V

Supply Current

50mA

Pin Count

Mounting

Surface Mount

Operating Temp Range

0C to 70C

Operating Temperature Classification

Commercial

Lead Free Status / RoHS Status

Supplier Unconfirmed

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The WS57C256F is a High Performance 32K x 8 UV Erasable EPROM. It is manufactured using an advanced

CMOS process technology enabling it to operate at speeds as fast as 35 ns Address Access Time (t

Chip Enable Time (t

low power device with a very cost effective die size. The low standby power capability of this 256 K product (200 µA

in a CMOS interface environment) is especially attractive.

This product, with its high speed capability, is particularly appropriate for use with today's fast DSP processors and

high-clock-rate Microprocessors. The WS57C256F's 35 ns speed enables these advanced processors to operate

without introducing any undesirable wait states. The WS57C256F is also ideal for use in modem applications, and is

recommended for use in these applications by the leading modem chip set manufacturer.

The WS57C256F is available in a variety of package types including the space saving 300 Mil DIP, the surface

mount PLDCC, and other windowed and non-windowed options. And its standard JEDEC EPROM pinouts provide

for automatic upgrade density paths for current 64K and 128K EPROM users.

MODE SELECTION

PRODUCT SELECTION GUIDE

NOTES:

1. X can be V

2. V

3. A1 – A8, A10 – A14 = V

MODE

Read

Output

Disable

Standby

Program

Verify

Program

Inhibit

Signature

Fast Access Time

— t

Low Power Consumption

— 200 µA Standby I

PARAMETER

Address Access Time (Max)

Output Enable Time (Max)

ACC

= V

PINS CE/

= 35 ns

Return to Main Menu

= 12.75 ± 0.25 V.

= 35 ns

PGM

V IH

V IL

or V

V IH

V IL

V IL V H

HIGH SPEED 32K x 8 CMOS EPROM

A 9

). It was designed utilizing WSI's patented self-aligned split gate EPROM cell, resulting in a

V IH V CC V CC

V IL V CC V CC

A 0

4. Manufacturer Signature.

5. Device Signature.

V PP

V CC V CC

V PP V CC OUTPUTS

WS57C256F-35

V CC

GENERAL DESCRIPTION

35 ns

15 ns

EO H

D OUT

High Z

D OUT

High Z

23 H

D IN

KEY FEATURES

WS57C256F-45

PIN CONFIGURATION

45 ns

20 ns

•

14 15 16 17 18 19 20

4 3 2

Immune to Latch-UP

— Up to 200 mA

ESD Protection Exceeds 2000 Volts

Available in 300 Mil DIP and PLDCC

DESC SMD No. 5962-86063

Chip Carrier

NC O

32 31 30

WS57C256F-55

TOP VIEW

55 ns

25 ns

CE/PGM

GND

WS57C256F

CERDIP

WS57C256F-70

ACC

70 ns

30 ns

) and 35 ns

A 14

A 13

A 8

A 9

A 11

A 10

CE/PGM

3-13

Related parts for WS57C256F-70J

WS57C256F-70J Summary of contents

Page 1

... The WS57C256F is available in a variety of package types including the space saving 300 Mil DIP, the surface mount PLDCC, and other windowed and non-windowed options. And its standard JEDEC EPROM pinouts provide for automatic upgrade density paths for current 64K and 128K EPROM users ...

Page 2

... WS57C256F ABSOLUTE MAXIMUM RATINGS* Storage Temperature............................–65° 150°C Voltage on any Pin with Respect to Ground ....................................–0.6V to +7V V and A with Respect to Ground ......–0. 14V PP 9 ESD Protection .................................................. OPERATING RANGE RANGE TEMPERATURE Commercial 0°C to +70°C Industrial –40°C to +85°C Military – ...

Page 3

... PP A.C. TESTING INPUT/OUTPUT WAVEFORM 3.0 2.0 0.8 0.0 A.C. testing inputs are driven at 3.0 V for a logic "1" and 0.0 V for a logic "0." Timing measurements are made at 2.0 V for a logic "1" and 0.8 V for a logic "0". WS57C256F MAX UNITS 2.0 ...

Page 4

... WS57C256F PROGRAMMING INFORMATION DC CHARACTERISTICS SYMBOLS Input Leakage Current Supply Current During Programming Pulse (CE/ PGM = Supply Current (Note Output Low Voltage During Verify mA) OL Output High Voltage During Verify –4 mA) OH NOTE must be applied either coincidentally or before must not be greater than 13 volts including overshoot. During CE = PGM = ...

Page 5

... WS57C256F-70CMB 70 WS57C256F-70D 70 * WS57C256F-70DMB 70 WS57C256F-70J 70 WS57C256F-70JI 70 WS57C256F-70T 70 NOTE: 11. The actual part marking will not include the initials "WS." * SMD product. See section 4 for DESC SMD number. PROGRAMMING/ALGORITHMS/ERASURE/PROGRAMMERS The WS57C256F is programmed using Algorithm D shown on page 5-9. When using Data I/O programmers, algorithm 57C256FB is recommended for use with the WS57C256F for best programming results ...

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