CY25245OXC Cypress Semiconductor Corp, CY25245OXC Datasheet - Page 5

• Manufacturer Part Number: CY25245OXC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY25245OXC

• Lead Free Status / RoHS Status: Compliant

Document #: 38-07124 Rev. *B
Serial Data Interface
The CY25245 features a two-pin, serial data interface that can
be used to configure internal register settings that control
particular device functions. Upon power-up, the CY25245
initializes with default register settings, therefore the use of this
serial data interface is optional. The serial interface is
write-only (to the clock chip) and is the dedicated function of
device pins SDATA and SCLOCK. In motherboard applica-
tions, SDATA and SCLOCK are typically driven by two logic
outputs of the chipset. Clock device register changes are
normally made upon system initialization, if any are required.
The interface can also be used during system operation for
Table 3. Serial Data Interface Control Functions Summary
Table 4. Byte Writing Sequence
Clock Output Disable Any individual clock output(s) can be disabled.
CPU Clock Frequency
Selection
Spread Spectrum
Enabling
Output three-state
(Reserved)
Sequence
Control Function
Byte
10
11
1
2
3
4
5
6
7
8
9
Slave Address
Command Code Don’t Care
Byte Count
Data Byte 0
Data Byte 1
Data Byte 2
Data Byte 3
Data Byte 4
Data Byte 5
Data Byte 6
Data Byte 7
Byte Name
Disabled outputs are actively held LOW.
Provides CPU/PCI frequency selections through
software. Frequency is changed in a smooth and
controlled fashion.
Enables or disables spread spectrum clocking.
Puts clock output into a high-impedance state.
Reserved function for future device revision or
production device testing.
11010010
Don’t Care
Refer to Table 5 The data bits in Data Bytes 0–7 set internal CY25245 registers that control device
Bit Sequence
Description
Unused by the CY25245, therefore bit values are ignored (“don’t care”). This byte
Unused by the CY25245, therefore bit values are ignored (“don’t care”). This byte
Commands the CY25245 to accept the bits in Data Bytes 0–6 for internal register
configuration. Since other devices may exist on the same common serial data
bus, it is necessary to have a specific slave address for each potential receiver.
The slave receiver address for the CY25245 is 11010010. Register setting will
not be made if the Slave Address is not correct (or is for an alternate slave
receiver).
must be included in the data write sequence to maintain proper byte allocation.
The Command Code Byte is part of the standard serial communication protocol
and may be used when writing to another addressed slave receiver on the serial
data bus.
must be included in the data write sequence to maintain proper byte allocation.
The Byte Count Byte is part of the standard serial communication protocol and may
be used when writing to another addressed slave receiver on the serial data bus.
operation. The data bits are only accepted when the Address Byte bit sequence
is 11010010, as noted above. For description of bit control functions, refer to
Table 5, Data Byte Serial Configuration Map.
power management functions. Table 3 summarizes the control
functions of the serial data interface.
Operation
Data is written to the CY25245 in eleven bytes of eight bits
each. Bytes are written in the order shown in Table 4.
Writing Data Bytes
Each bit in Data Bytes 0–7 control a particular device function
except for the “reserved” bits which must be written as a logic
0. Bits are written MSB (most significant bit) first, which is bit 7.
Table 5 gives the bit formats for registers located in Data Bytes
0–7.
Unused outputs are disabled to reduce EMI and
system power. Examples are clock outputs to unused
PCI slots.
For alternate microprocessors and power
management options. Smooth frequency transition
allows CPU frequency change under normal system
operation.
No user application. Register bit must be written as 0.
For EMI reduction.
Production PCB testing.
Byte Description
Common Application
CY25245
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