AD9430-LVDS/PCBZ Analog Devices Inc, AD9430-LVDS/PCBZ Datasheet - Page 13

• Manufacturer Part Number: AD9430-LVDS/PCBZ
• Manufacturer: Analog Devices Inc

Specifications of AD9430-LVDS/PCBZ

• Lead Free Status / RoHS Status: Compliant

Table 8. LVDS Mode Pin Function Descriptions
Pin Number
1
2, 42 to 46
3
4, 9, 12, 13, 16, 17, 20, 23, 25, 26, 30, 31, 35, 38, 41, 86, 87, 91,
92, 93, 96, 97, 100
5
6
7
8, 14, 15, 18, 19, 24, 27, 28, 29, 33, 34, 39, 40, 88, 89, 90, 94, 95,
98, 99
10
11
21
22
32
36
37
LVDSBIAS
SENSE
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AVDD
AVDD
AVDD
AVDD
AVDD
AVDD
VREF
VIN+
VIN–
DNC
S5
S4
S2
S1
10
11
12
13
14
15
16
17
18
19
20
22
23
24
25
21
1
2
3
4
5
6
7
8
9
Figure 5. LVDS Mode Pin Configuration
Rev. D | Page 13 of 44
Mnemonic
S5
DNC
S4
AGND
S2
S1
LVDSBIAS
AVDD
SENSE
VREF
VIN+
VIN–
GND
CLK+
CLK–
LVDS PINOUT
(Not to Scale)
AD9430
TOP VIEW
2
1
Full-Scale Adjust Pin. AVDD sets f
GND sets f
Do Not Connect.
Control Pin for CMOS Mode. Tie low when operating in LVDS
mode.
Analog Ground.
Output Mode Select. GND = dual-port CMOS; AVDD = LVDS.
Data Format Select. GND = binary, AVDD = twos complement.
Set Pin for LVDS Output Current. Place 3.74 kW resistor
terminated to ground.
3.3 V Analog Supply.
Reference Mode Select Pin. Float for internal reference
operation.
1.235 V Reference I/O—Function Dependent on SENSE.
Analog Input—True.
Analog Input—Complement.
Data Sync (Input)—Not Used in LVDS Mode. Tie to GND.
Clock Input—True (LVPECL Levels).
Clock Input—Complement (LVPECL Levels).
Description
S
= 1.536 V p-p differential.
69 D6+
75 DRVDD
74 DRGND
73 D8+
72 D8–
71 D7+
70 D7–
68 D6–
67 DRGND
66 D5+
65 D5–
64 DCO+
63 DCO–
62 DRVDD
61 DRGND
60 D4+
59 D4–
58 D3+
57 D3–
56 D2+
55
54
53
52
51
D2–
DRVDD
DRGND
D1+
D1–
S
= 0.768 V p-p differential,
AD9430