LFX125EB-04F256I LATTICE SEMICONDUCTOR, LFX125EB-04F256I Datasheet - Page 7

• Manufacturer Part Number: LFX125EB-04F256I
• Description: FPGA ispXPGA® Family 139K Gates 1936 Cells EECMOS Technology 2.5V/3.3V 256-Pin FBGA
• Manufacturer: LATTICE SEMICONDUCTOR

Specifications of LFX125EB-04F256I

• Package: 256FBGA
• Family Name: ispXPGA®
• Device Logic Units: 1936
• Device System Gates: 139000
• Number Of Registers: 3800
• Typical Operating Supply Voltage: 2.5|3.3 V
• Maximum Number Of User I/os: 160
• Ram Bits: 94208
• Re-programmability Support: Yes

Lattice Semiconductor
ispXPGA Family Data Sheet
Architecture Overview
The ispXPGA architecture is a symmetrical architecture consisting of an array of Programmable Function Units
(PFUs) enclosed by Input Output Groups (PICs) with columns of sysMEM Embedded Block RAMs (EBRs) distrib-
uted throughout the array. Figure 1 illustrates the ispXPGA architecture. Each PIC has two corresponding sysIO
blocks, each of which includes one input and output buffer. On two sides of the device, between the PICs and the
sysIO blocks, there are sysHSI High-Speed Interface blocks. The symmetrical architecture allows designers to eas-
ily implement their designs, since any logic function can be placed in any section of the device.
The PFUs contain the basic building blocks to create logic, memory, arithmetic, and register functions. They are
optimized for speed and flexibility allowing complex designs to be implemented quickly and efficiently.
The PICs interface the PFUs and EBRs to the external pins of the device. They allow the signals to be registered
quickly to minimize setup times for high-speed designs. They also allow connections directly to the different logic
elements for fast access to combinatorial functions.
The sysMEM EBRs are large, fast memory elements that can be configured as RAM, ROM, FIFO, and other stor-
age types. They are designed to facilitate both single and dual-port memory for high-speed applications.
These three components of the architecture are interconnected via a high-speed, flexible routing array. The routing
array consists of Variable Length Interconnect (VLI) lines between the PICs, PFUs, and EBRs. There is additional
routing available to the PFU for feedback and direct routing of signals to adjacent PFUs or PICs.
The sysIO blocks consist of configurable input and output buffers connected directly to the PICs. These buffers can
be configured to interface with 16 different I/O standards. This allows the ispXPGA to interface with other devices
without the need for external transceivers.
The sysHSI blocks provide the necessary components to allow the ispXPGA device to transfer data at up to
800Mbps using the LVDS standard. These components include serializing, de-serializing, and clock data recovery
(CDR) logic.
The sysCLOCK blocks provide clock multiplication/division, clock distribution, delay compensation, and increased
performance through the use of PLL circuitry that manipulates the global clocks. There is one sysCLOCK block for
each global clock tree in the device.
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