LFXP20C-5FN256C LATTICE SEMICONDUCTOR, LFXP20C-5FN256C Datasheet - Page 11
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LFXP20C-5FN256C
Manufacturer Part Number
LFXP20C-5FN256C
Description
FPGA LatticeXP Family 20000 Cells 400MHz 130nm (CMOS) Technology 1.8V/2.5V/3.3V 256-Pin FBGA Tray
Manufacturer
LATTICE SEMICONDUCTOR
Datasheet
1.LFXP3C-3QN208C.pdf
(130 pages)
Specifications of LFXP20C-5FN256C
Package
256FBGA
Family Name
LatticeXP
Device Logic Units
20000
Maximum Internal Frequency
400 MHz
Typical Operating Supply Voltage
1.8|2.5|3.3 V
Maximum Number Of User I/os
188
Ram Bits
405504
Re-programmability Support
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LFXP20C-5FN256C
Manufacturer:
PULSE
Quantity:
695
Company:
Part Number:
LFXP20C-5FN256C
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
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Lattice Semiconductor
Figure 2-6. Secondary Clock Sources
Clock Routing
The clock routing structure in LatticeXP devices consists of four Primary Clock lines and a Secondary Clock net-
work per quadrant. The primary clocks are generated from MUXs located in each quadrant. Figure 2-7 shows this
clock routing. The four secondary clocks are generated from MUXs located in each quadrant as shown in Figure 2-
8. Each slice derives its clock from the primary clock lines, secondary clock lines and routing as shown in Figure 2-
9.
Figure 2-7. Per Quadrant Primary Clock Selection
Clock Input
From Routing
From Routing
From Routing
From Routing
1. Smaller devices have fewer PLL related lines.
2. Dynamic clock select.
4 Primary Clocks (CLK0, CLK1, CLK2, CLK3) per Quadrant
20 Primary Clock Sources: 12 PLLs + 4 PIOs + 4 Routing
Routing
Routing
From
From
Routing
Routing
20 Secondary Clock Sources
To Quadrant Clock Selection
From
From
Clock
Clock
Input
Input
DCS
2-8
2
Routing
Routing
From
From
Routing
Routing
From
From
LatticeXP Family Data Sheet
DCS
1
2
From Routing
From Routing
From Routing
From Routing
Clock Input
Architecture
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