LFXP3C-3QN208I LATTICE SEMICONDUCTOR, LFXP3C-3QN208I Datasheet - Page 5

• Manufacturer Part Number: LFXP3C-3QN208I
• Description: FPGA LatticeXP Family 3000 Cells 320MHz 130nm (CMOS) Technology 1.8V/2.5V/3.3V 208-Pin PQFP Tray
• Manufacturer: LATTICE SEMICONDUCTOR

Specifications of LFXP3C-3QN208I

• Package: 208PQFP
• Family Name: LatticeXP
• Device Logic Units: 3000
• Maximum Internal Frequency: 320 MHz
• Typical Operating Supply Voltage: 1.8|2.5|3.3 V
• Maximum Number Of User I/os: 136
• Ram Bits: 55296
• Re-programmability Support: Yes

Lattice Semiconductor
Figure 2-1. LatticeXP Top Level Block Diagram
PFU and PFF Blocks
The core of the LatticeXP devices consists of PFU and PFF blocks. The PFUs can be programmed to perform
Logic, Arithmetic, Distributed RAM and Distributed ROM functions. PFF blocks can be programmed to perform
Logic, Arithmetic and ROM functions. Except where necessary, the remainder of the data sheet will use the term
PFU to refer to both PFU and PFF blocks.
Each PFU block consists of four interconnected slices, numbered 0-3 as shown in Figure 2-2. All the interconnec-
tions to and from PFU blocks are from routing. There are 53 inputs and 25 outputs associated with each PFU block.
Figure 2-2. PFU Diagram
sysCONFIG Programming
Port (includes dedicated
and dual use pins)
Non-volatile Memory
Programmable
Functional Unit (PFU)
Latch
FF/
LUT4 &
CARRY
D
Programmable I/O Cell
(PIC) includes sysIO
Interface
Slice 0
Latch
FF/
LUT4 &
CARRY
D
Latch
FF/
LUT4 &
CARRY
D
Slice 1
Latch
FF/
LUT4 &
CARRY
D
Routing
Routing
From
2-2
To
Latch
FF/
LUT4 &
CARRY
D
Slice 2
Latch
FF/
CARRY
LUT4 &
D
LatticeXP Family Data Sheet
Latch
FF/
LUT4 &
CARRY
D
Slice 3
Latch
FF/
LUT4 &
CARRY
D
JTAG Port
sysCLOCK PLL
sysMEM Embedded
Block RAM (EBR)
PFF (PFU without
RAM)
Architecture