RFM31B-868-S1 QUASAR, RFM31B-868-S1 Datasheet - Page 23

• Manufacturer Part Number: RFM31B-868-S1
• Description: MODULE, RECEIVER, -118DB, SMD,868MHZ
• Manufacturer: QUASAR

Specifications of RFM31B-868-S1

• Modulation Type: FSK, GFSK, OOK
• Sensitivity: -121dBm
• Power Supply: 1.8V To 3.6V
• Supply Current: 18.5mA
• Data Rate Max: 256Kbps
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

RFM31B
When AFC is enabled, the preamble length needs to be long enough to settle the AFC. In general, one byte of
preamble is sufficient to settle the AFC. Disabling the AFC allows the preamble to be shortened from 40 bits to 32
bits. Note that with the AFC disabled, the preamble length must still be long enough to settle the receiver and to
detect the preamble (see "6.6. Preamble Length" ). The AFC corrects the detected frequency offset by
changing the frequency of the Fractional-N PLL. When the preamble is detected, the AFC will freeze for the
remainder of the packet. In multi-packet mode, the AFC is reset at the end of every packet and will re-acquire the
frequency offset for the next packet. The AFC loop includes a bandwidth limiting mechanism improving the
rejection of out of band signals. When the AFC loop is enabled, its pull-in-range is determined by the bandwidth
limiter value (AFCLimiter) which is located in register 2Ah.
AFC_pull_in_range = ±AFCLimiter[7:0] x (hbsel+1) x 625 Hz
The AFC Limiter register is an unsigned register and its value can be obtained from the Register Calculator
spreadsheet.
Frequency Correction
AFC disabled
Freq Offset Register
AFC enabled
AFC
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