72V73273BBG IDT, Integrated Device Technology Inc, 72V73273BBG Datasheet - Page 8

• Manufacturer Part Number: 72V73273BBG
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of 72V73273BBG

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 208
• Lead Free Status / RoHS Status: Compliant

TABLE 3
IDT72V73273 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH WITH RATE MATCHING 32,768 x 32,768 CHANNELS
Reset Value:
BIT
7-5
1-0
15
14
13
12
11
10
9
8
4
3
2
SRS
15
SRS
(Software Reset)
BYP
(RX/TX Bypass)
OEPOL
(Output Enable Polarity)
AOE
(All Output Enable)
PRST
(PRBS Reset)
CBER
(Clear Bit Error Rate)
SBER
(Start Bit Error Rate)
FBP
(Full Block Programming)
BPD2-0
(Block Programming Data) feature is activated. After the BPE bit is set to 1 from 0, the contents of the bits BPD2-0 are loaded into bit 2, 1 and 0 (MOD2-0)
BPE
(Begin Block
Programming Enable)
RCML
(Reset Connection
Memory LOW in Block
Programming)
OSB
(Output Standby)
MS1-0
(Memory Select)
NAME
BYP
14
CONTROL REGISTER (CR) BITS
0000
OEPOL
13
H
AOE
12
sets the TSI to a 1-to-1 switch mode with almost only a few nanoseconds of delay. A zero can be written to allow normal operation.
These two bits decide which memory to be accessed via microprocessor port.
When the Bypass bit is 1, all RX streams will be “shorted” to TX -- in effect bypassing all internal circuitry of the TSI. This effectively
The intention of this mode is to minimize the delay from the RX input to the TX output making the TSI “invisible”. Any offset values
in the FOR register will be required.
When 1, a one on OEI pin denotes an active state on the output data stream; zero on OEI pin denotes High-Impedance state.
When 0, a one denotes High-Impedance and a zero denotes an active state. OEI mode is entered on a per-group basis in the
DRSR.
When 1, all output stream pin (TXn) become OEI to allow for a two-chip solution for a larger switching matrix with OEI pins. When
in AOE the DRS must be set to the corresponding data rates of the other device.
When HIGH, the PRBS transmitter output will be initialized.
A low to high transition of this bit clears the BER register (BERR).
A low to high transition in this bit starts the bit error rate test. The bit error test result is kept in the BER register (BERR).
When 1, this bit overrides the BPSA and BPEA registers and programs the full Connection Memory space. When 0, the BPSA
and BPEA determine the Connection Memory space to be programmed.
These bits carry the value to be loaded into the Connection Memory block whenever the Connection Memory block programming
of the Connection Memory HIGH.
A zero to one transition of this bit enables the Connection Memory block programming feature delimited by the BPSA and BPEA
registers as well as for a full back program. Once the BPE bit is set HIGH, the device will program the Connection Memory block
as fast as than if the user manually programmed each Connection Memory location through the microprocessor. After the programming
function has finished, the BPE bit returns to zero to indicate the operation has completed. When the BPE = 1, the BPE bit can be
set to 0 to abort block programming.
When RCML =1, all bits 14-0 in Connection Memory LOW will be reset to zero during block programming; when RCML=0,
bits 14-0 in Connection Memory LOW will retain their original values during block programming.
When ODE = 0 and OSB = 0, the output drivers of transmit serial streams are in High-Impedance mode. When either ODE = 1
A one will reset the device and have the same effect as the RESET pin. Must be zero for normal operation.
or OSB = 1, the output serial stream drivers function normally.
00 -- Connection Memory LOW
01 -- Connection Memory HIGH
10 -- Data Memory
11 -- Reserved
PRST
11
`
CBER
10
DESCRIPTION
SBER
9
FBP
8
8
BPD2
7
BPD1
6
BPD0
5
BPE
4
INDUSTRIAL TEMPERATURE RANGE
RCML
3
OSB
2
MS1
1
MS0
0