DS90CR214MTDX National Semiconductor, DS90CR214MTDX Datasheet - Page 4

• Manufacturer Part Number: DS90CR214MTDX
• Manufacturer: National Semiconductor

Specifications of DS90CR214MTDX

• Number Of Elements: 3
• Input Type: CMOS/TTL
• Operating Supply Voltage (typ): 5V
• Differential Output Voltage: 450mV
• Power Dissipation: 1.98W
• Operating Temp Range: -10C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 48
• Package Type: TSSOP
• Number Of Receivers: 3
• Number Of Drivers: 21
• Lead Free Status / RoHS Status: Not Compliant

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TRANSMITTER SUPPLY CURRENT
RECEIVER SUPPLY CURRENT
I
I
LLHT
LHLT
TCIT
TCCS
TPPos0
TPPos1
TPPos2
TPPos3
TPPos4
TPPos5
TPPos6
TCIP
TCIH
TCIL
TSTC
THTC
TCCD
TPLLS
TPDD
CLHT
CHLT
CCRW
CCRZ
Symbol
Symbol
Symbol
Electrical Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device
should be operated at these limits. The tables of “Electrical Characteristics” specify conditions for device operation.
Note 2: Typical values are given for V
Note 3: Current into device pins is defined as positive. Current out of device pins is defined as negative. Voltages are referenced to ground unless otherwise
specified (except V
Note 4: ESD Rating: HBM (1.5 kΩ, 100 pF)
Note 5: V
Transmitter Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified
Note 6: This limit based on bench characterization.
Receiver Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified
PLL V
All Other Pins ≥ 2000V
EIAJ (0Ω, 200 pF) ≥ 150V
CC
OS
LVDS Low-to-High Transition Time (Figure 2 )
LVDS High-to-Low Transition Time (Figure 2 )
TxCLK IN Transition Time (Figure 4 )
TxOUT Channel-to-Channel Skew (Note 6) (Figure 5)
Transmitter Output Pulse Position for Bit 0 (Figure 16 )
Transmitter Output Pulse Position for Bit 1
Transmitter Output Pulse Position for Bit 2
Transmitter Output Pulse Position for Bit 3
Transmitter Output Pulse Position for Bit 4
Transmitter Output Pulse Position for Bit 5
Transmitter Output Pulse Position for Bit 6
TxCLK IN Period (Figure 6 )
TxCLK IN High Time (Figure 6 )
TxCLK IN Low Time (Figure 6 )
TxIN Setup to TxCLK IN (Figure 6 )
TxIN Hold to TxCLK IN (Figure 6 )
TxCLK IN to TxCLK OUT Delay
Transmitter Phase Lock Loop Set (Figure 10 )
Transmitter Powerdown Delay (Figure 14 )
≥ 1000V
Power Down
Receiver Supply Current
Worst Case
Receiver Supply Current
Power Down
CMOS/TTL Low-to-High Transition Time (Figure 3 )
CMOS/TTL High-to-Low Transition Time (Figure 3 )
previously referred as V
OD
and ∆V
Parameter
OD
).
CM
CC
.
= 5.0V and T
@
Parameter
25˚C, V
A
(Continued)
= +25˚C.
Parameter
Driver Outputs in TRI-STATE under
Powerdown Mode
C
Worst Case Pattern
(Figure 1 and Figure 3 )
Powerdown = Low
Receiver Outputs in Previous State during
Power Down Mode.
L
= 8 pF,
CC
= 5.0V (Figure 8 )
Conditions
4
f = 32.5 MHz
f = 37.5 MHz
f = 66 MHz
f = 66 MHz
−0.30
10.40
12.70
0.35T
0.35T
1.70
3.60
5.90
8.30
Min
2.5
3.5
15
5
Min
Min
(1/7)Tclk
(2/7)Tclk
(3/7)Tclk
(4/7)Tclk
(5/7)Tclk
(6/7)Tclk
0.75
0.75
0.5T
0.5T
Typ
3.5
1.5
Typ
110
Typ
64
70
0
T
2.5
2.0
1
1
Max
Max
11.10
13.40
0.65T
0.65T
140
4.0
4.0
Max
0.30
2.50
4.50
6.75
9.00
77
85
10
25
350
100
1.5
1.5
8.5
50
10
8
Units
Units
Units
mA
mA
mA
ns
ns
µA
µA
ms
ns
ns
ns
ps
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns