NB6L572MMNG ON Semiconductor, NB6L572MMNG Datasheet - Page 6

• Manufacturer Part Number: NB6L572MMNG
• Manufacturer: ON Semiconductor

Specifications of NB6L572MMNG

• Lead Free Status / RoHS Status: Compliant

NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
11. Measured using a 100 mVpk−pk source, 50% duty cycle clock source. All output loading with external 50 W to V
12. Output voltage swing is a single−ended measurement operating in differential mode.
13. Skew is measured between outputs under identical transitions and conditions. Duty cycle skew is defined only for differential operation when
14. Additive RMS jitter with 50% duty cycle clock signal.
15. Additive Peak−to−Peak data dependent jitter with input NRZ data at PRBS23.
16. Crosstalk is measured at the output while applying two similar clock frequencies that are asynchronous with respect to each other at the
17. Input voltage swing is a single−ended measurement operating in differential mode.
Table 6. AC CHARACTERISTICS
f
f
f
V
t
t
t
Tempco
tskew
t
F
t
t
V
t
Symbol
MAX
DATAMAX
SEL
PLH
PHL
PD
DC
JITTER
r,
OUTPP
FN
INPP
, t
N
40 ps (20% − 80%).
the delays are measured from cross−point of the inputs to the cross−point of the outputs.
inputs.
Figure 3. Clock Output Voltage Amplitude (V
f
,
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
Maximum Input Clock Frequency V
Maximum Operating Data Rate NRZ, (PRBS23)
Maximum Toggle Frequency, SELx
Output Voltage Amplitude (@ V
(Note 12) (Figure 10)
Propagation Delay to Differential Outputs
Measured at Differential Crosspoint
Differential Propagation Delay Temperature Coefficient
Output – Output skew (within device) (Note 13)
Device – Device skew (tpdmax – tpdmin)
Output Clock Duty Cycle (Reference Duty Cycle = 50%) f
Phase Noise, fin = 1 GHz
Integrated Phase Jitter (Figure x) fin = 1 GHz, 12 kHz * 20 MHz Offset
(RMS)
Random Clock Jitter, RJ(RMS) (Note 14)
Deterministic Jitter, DJ (Note 15) (FR4 ≤ 12’)
Crosstalk Induced Jitter (Adjacent Channel) (Note 16)
Input Voltage Swing (Differential Configuration) (Note 17)
Output Rise/Fall Times @ 1 GHz; (20% − 80%), V
600
500
400
300
200
100
0
V
0
CC
Characteristic
INPPmin
= 2.375 V to 3.6 V, GND = 0 V, T
Q AMP (mV)
1
OUT
f
in
, CLOCK INPUT FREQUENCY (GHz)
) f
w 250 mV
in
2
≤ 5 GHz
OUTPP
http://onsemi.com
3
@ 1 GHz INx/INx to Qx/Qx
@ 50 MHz SELx to Qx
IN
) vs. Input Frequency (f
= 400 mV Qx, Qx
6
4
in
f
in
= 1 GHz
f
≤ 6.5 Gbps
in
100 kHz
≤ 5 GHz
5
10 MHz
20 MHz
40 MHz
A
10 kHz
1 MHz
= −40°C to +85°C (Note 11)
6
7
in
) at Ambient Temperature (Typical)
Min
250
125
100
6.5
20
45
20
5
8
−134
−136
−149
−150
−150
−150
0.35
Typ
400
200
100
0.2
40
50
35
35
6
8
4
0
5
1
CC
1200
Max
250
0.8
0.7
10
15
25
55
50
. Input edge rates
5
ps pk−pk
ps RMS
ps RMS
Dfs/°C
Gbps
GHz
MHz
Unit
dBc
mV
mV
ps
ns
ps
ps
%
fs