87021AMILFT IDT, Integrated Device Technology Inc, 87021AMILFT Datasheet - Page 9

• Manufacturer Part Number: 87021AMILFT
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Clock Dividerr

Specifications of 87021AMILFT

• Number Of Clock Inputs: 1
• Mode Of Operation: Differential
• Output Frequency: 250MHz
• Output Logic Level: LVCMOS/LVTTL
• Operating Supply Voltage (min): 2.375V
• Operating Supply Voltage (typ): 2.5/3.3V
• Operating Supply Voltage (max): 3.465V
• Package Type: SOIC N
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 8
• Lead Free Status / RoHS Status: Compliant

D
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL
and other differential signals. Both signals must meet the V
V
for the HiPerClockS CLK/nCLK input driven by the most common
driver types. The input interfaces suggested here are examples
F
F
IDT
F
CMR
IGURE
IGURE
IGURE
IFFERENTIAL
ICS87021I
÷1/÷2 DIFFERENTIAL-TO-LVCMOS/LVTTL CLOCK GENERATOR
™
3.3V
input requirements. Figures 2A to 2E show interface examples
R5,R6 locate near the driver pin.
/ ICS
3.3V
LVPECL
2C. H
2A. H
2E. H
1.8V
™
LVPECL
LVCMOS CLOCK GENERATOR
R5
100 - 200
LVHSTL
ICS
HiPerClockS
LVHSTL Driver
3.3V LVPECL D
IDT H
3.3V LVPECL D
I
I
I
P
P
P
C
ER
ER
ER
LOCK
Zo = 50 Ohm
Zo = 50 Ohm
R6
100 - 200
C
Zo = 50 Ohm
Zo = 50 Ohm
C
I
C
P
LOCK
Zo = 50 Ohm
Zo = 50 Ohm
LOCK
LOCK
ER
C
I
NPUT
LOCK
S CLK/nCLK I
S CLK/nCLK I
S CLK/nCLK I
RIVER
S LVHSTL D
RIVER WITH
R1
50
3.3V
R3
125
C1
C2
I
NTERFACE
R1
84
R2
50
3.3V
R3
125
R4
125
R1
84
R2
84
CLK
nCLK
R4
125
NPUT
R2
84
AC C
NPUT
CLK
nCLK
NPUT
3.3V
3.3V
RIVER
HiPerClockS
Input
HiPerClockS
Input
D
D
D
OUPLE
CLK
nCLK
RIVEN BY
RIVEN BY
RIVEN BY
3.3V
HiPerClockS
Input
PP
and
9
F
only. Please consult with the vendor of the driver component to
confirm the driver termination requirements. For example in Figure
2A, the input termination applies for IDT HiPerClockS LVHSTL
drivers. If you are using an LVHSTL driver from another vendor,
use their termination recommendation.
F
IGURE
IGURE
3.3V
3.3V
2D. H
2B. H
LVDS_Driv er
LVPECL
3.3V LVPECL D
3.3V LVDS D
I
I
P
P
Zo = 50 Ohm
Zo = 50 Ohm
ER
ER
C
C
LOCK
LOCK
Zo = 50 Ohm
Zo = 50 Ohm
S CLK/nCLK I
S CLK/nCLK I
ICS87021AMI REV. B AUGUST 26, 2008
RIVER
R1
50
RIVER
R3
50
R2
50
R1
100
CLK
nCLK
3.3V
NPUT
NPUT
HiPerClockS
Input
CLK
nCLK
D
D
3.3V
RIVEN BY
RIVEN BY
Receiv er