8536AG-01 IDT, Integrated Device Technology Inc, 8536AG-01 Datasheet - Page 10

• Manufacturer Part Number: 8536AG-01
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Clock Driverr

Specifications of 8536AG-01

• Number Of Clock Inputs: 3
• Output Frequency: 700MHz
• Output Logic Level: LVPECL
• Operating Supply Voltage (min): 2.375V
• Operating Supply Voltage (typ): 2.5/3.3V
• Operating Supply Voltage (max): 3.465V
• Package Type: TSSOP
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 24
• Lead Free Status / RoHS Status: Not Compliant

W
Figure 1 shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF = V
generated by the bias resistors R1, R2 and C1. This bias circuit
should be located as close as possible to the input pin. The ratio
R
I
C
For applications not requiring the use of the crystal oscillator input,
both XTAL_IN and XTAL_OUT can be left floating. Though not
required, but for additional protection, a 1k
from XTAL_IN to ground.
CLK I
For applications not requiring the use of the clock, it can be left
floating. Though not required, but for additional protection, a 1k
resistor can be tied from the CLK input to ground.
CLK/nCLK I
For applications not requiring the use of the differential input,
both CLK and nCLK can be left floating. Though not required, but
for additional protection, a 1k
ground.
LVCMOS C
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional
protection. A 1k
IDT
NPUTS
RYSTAL
ECOMMENDATIONS FOR
ICS8536-01
LOW SKEW, 1-TO-6, CRYSTAL/LVCMOS/DIFFERENTIAL-TO-3.3V, 2.5V LVPECL FANOUT BUFFER
IRING THE
™
/ ICS
NPUT
:
I
NPUTS
™
3.3V, 2.5V LVPECL FANOUT BUFFER
ONTROL
NPUTSA
D
IFFERENTIAL
resistor can be used.
P
INS
U
NUSED
I
NPUT TO
resistor can be tied from CLK to
F
IGURE
I
NPUT AND
Single Ended Clock Input
A
CCEPT
1. S
A
resistor can be tied
PPLICATION
INGLE
O
S
UTPUT
INGLE
E
C1
0.1u
NDED
V_REF
CC
E
/2 is
P
NDED
S
INS
IGNAL
10
I
L
NFORMATION
of R1 and R2 might need to be adjusted to position the V_REF in
the center of the input voltage swing. For example, if the input
clock swing is only 2.5V and V
and R2/R1 = 0.609.
O
LVPECL O
All unused LVPECL outputs can be left floating. We recommend
that there is no trace attached. Both sides of the differential output
pair should either be left floating or terminated.
D
EVELS
1K
R1
1K
R2
UTPUTS
RIVING
VCC
D
CLK
nCLK
:
UTPUTS
IFFERENTIAL
ICS8536AG-01 REV. A FEBRUARY 24, 2009
I
NPUT
CC
= 3.3V, V_REF should be 1.25V