ICS8536CGI-33T IDT, Integrated Device Technology Inc, ICS8536CGI-33T Datasheet - Page 11

• Manufacturer Part Number: ICS8536CGI-33T
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Clock Driverr

Specifications of ICS8536CGI-33T

• Number Of Clock Inputs: 2
• Mode Of Operation: Single-Ended
• Output Frequency: 266MHz
• Operating Supply Voltage (min): 2.375V
• Operating Supply Voltage (typ): 2.5/3.3V
• Operating Supply Voltage (max): 3.465V
• Package Type: TSSOP
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 20
• Lead Free Status / RoHS Status: Not Compliant

LVCMOS
The XTAL_IN input can accept a single-ended LVCMOS signal
through an AC coupling capacitor. A general interface diagram is
shown in Figure 3. The XTAL_OUT pin can be left floating. The
input edge rate can be as slow as 10ns. For LVCMOS inputs, it is
recommended that the amplitude be reduced from full swing to
half swing in order to prevent signal interference with the power
rail and to reduce noise. This configuration requires that the output
T
The clock layout topology shown below is a typical termination
for LVPECL outputs. The two different layouts mentioned are
recommended only as guidelines.
FOUT and nFOUT are low impedance follower outputs that
generate ECL/LVPECL compatible outputs. Therefore, termi-
nating resistors (DC current path to ground) or current sources
must be used for functionality. These outputs are designed to
IDT
RTT =
ERMINATION FOR
ICS8536I-33
LOW SKEW, 1-TO-6, CRYSTAL OSCILLATOR/LVCMOS-TO-3.3V, 2.5V LVPECL/LVCMOS FANOUT BUFFER
™
/ ICS
((V
F
™
FOUT
IGURE
OH
3.3V, 2.5V LVPECL/ LVCMOS FANOUT BUFFER
+ V
TO
OL
4A. LVPECL O
XTAL I
) / (V
1
3.3V LVPECL O
CC
Z
Z
– 2)) – 2
o
o
= 50
= 50
NTERFACE
F
IGURE
Z
o
50
UTPUT
3. G
VDD
Ro
T
ENERAL
RTT
ERMINATION
UTPUTS
50
V
CC
D
IAGRAM FOR
FIN
- 2V
Rs
Zo = Ro + Rs
Zo = 50
LVCMOS D
11
impedance of the driver (Ro) plus the series resistance (Rs) equals
the transmission line impedance. In addition, matched termination
at the crystal input will attenuate the signal in half. This can be
done in one of two ways. First, R1 and R2 in parallel should equal
the transmission line impedance. For most 50
and R2 can be 100 . This can also be accomplished by removing
R1 and making R2 50 .
drive 50
should be used to maximize operating frequency and minimize
signal distortion. Figures 4A and 4B show two different layouts
which are recommended only as guidelines. Other suitable
clock layouts may exist and it would be recommended that the
board designers simulate to guarantee compatibility across all
printed circuit and clock component process variations.
VDD
FOUT
RIVER TO
R1
R2
F
IGURE
.1uf
transmission lines. Matched impedance techniques
XTAL I
4B. LVPECL O
XTAL_IN
XTAL_OUT
Z
Z
o
o
= 50
= 50
NPUT
ICS8536CGI-33 REV. B OCTOBER 27, 2008
125
I
NTERFACE
84
UTPUT
3.3V
125
84
T
ERMINATION
FIN
applications, R1