889874AK IDT, Integrated Device Technology Inc, 889874AK Datasheet

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889874AK

Manufacturer Part Number
889874AK
Description
Manufacturer
IDT, Integrated Device Technology Inc
Type
Clock Dividerr
Datasheet

Specifications of 889874AK

Number Of Clock Inputs
1
Mode Of Operation
Differential
Output Frequency
2000MHz
Output Logic Level
ECL/LVPECL
Operating Supply Voltage (min)
-2.375/2.375V
Operating Supply Voltage (typ)
-2.5/-3.3/3.3V
Package Type
VFQFN
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Signal Type
CML/LVDS/LVPECL
Mounting
Surface Mount
Pin Count
16
Lead Free Status / RoHS Status
Not Compliant
B
nRESET
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
889874AK
G
which allows the device to be used as either a 1:2 fanout
buffer or frequency divider. The clock input has internal
termination resistors, allowing it to interface with several
differential signal types while minimizing the number of
required external components. The device is packaged in
a small, 3mm x 3mm VFQFN package, making it ideal for
use on space-constrained boards.
HiPerClockS™
IC S
V
LOCK
REF_AC
ENERAL
nIN
S2
S0
S1
IN
V
T
D
The ICS889874 is a high speed 1:2 Differential-
to-LVPECL Buffer/Divider and is a member of
the HiPerClockS
clock solutions from ICS. The ICS889874 has
a selectable ÷1, ÷2, ÷4, ÷8, ÷16 output divider,
Decoder
IAGRAM
Integrated
Circuit
Systems, Inc.
D
ESCRIPTION
Enable
FF
family of high performance
00 ÷2
01 ÷4
10 ÷8
11 ÷16
Enable
MUX
www.icst.com/products/hiperclocks.html
PRELIMINARY
0
1
1
F
• Two LVPECL outputs
• Frequency divide select options: ÷ 1, ÷ 2, ÷4, ÷8, ÷16
• IN, nIN input can accept the following differential input levels:
• Output frequency: > 2.5GHz
• Output skew: 5ps (typical)
• Part-to-part skew: TBD
• Additive jitter, RMS: <0.03ps (design target)
• Supply voltage range: (LVPECL), 2.375V to 3.465V
• -40°C to 85°C ambient operating temperature
• Available in both standard and lead-free RoHS compliant
D
LVPECL, LVDS, CML
Supply voltage range: (ECL), -3.465V to -2.375V
packages
EATURES
IFFERENTIAL
Q0
nQ0
Q1
nQ1
-
TO
-LVPECL B
P
3mm x 3mm x 0.95 package body
IN
nQ0
nQ1
Q0
Q1
A
16-Lead VFQFN
1
2
3
4
SSIGNMENT
ICS889874
16 15 14 13
5
K Package
ICS889874
Top View
6
UFFER
7
REV. A MARCH 20, 2006
8
12
11
10
9
/D
IN
V
V
nIN
T
REF
IVIDER
_
AC
1:2

Related parts for 889874AK

889874AK Summary of contents

Page 1

... Decoder S1 V REF_AC The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice. 889874AK PRELIMINARY D IFFERENTIAL F EATURES • Two LVPECL outputs • ...

Page 2

... Integrated Circuit Systems, Inc ABLE IN ESCRIPTIONS ABLE IN HARACTERISTICS 889874AK PRELIMINARY D IFFERENTIAL www.icst.com/products/hiperclocks.html 2 ICS889874 - -LVPECL UFFER Ω REV. A MARCH 20, 2006 1:2 IVIDER kΩ ...

Page 3

... Integrated Circuit Systems, Inc ABLE ONTROL NPUT UNCTION nRESET nIN IGURE T 3B ABLE RUTH ABLE 889874AK PRELIMINARY D IFFERENTIAL T ABLE nRESET IMING IAGRAM WHEN ÷ ÷ ÷ ÷ www.icst.com/products/hiperclocks.html 3 ICS889874 - -LVPECL UFFER Swing OUT REV. A MARCH 20, 2006 1:2 IVIDER ...

Page 4

... 889874AK PRELIMINARY D IFFERENTIAL NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage + 0 the device. These ratings are stress specifi- 50mA cations only. Functional operation of product at 100mA these conditions or any conditions beyond those listed in the DC Characteristics or AC Character- istics is not implied ...

Page 5

... Systems, Inc. T 4D. LVPECL DC C ABLE HARACTERISTICS Ω 3.3V±10% ABLE HARACTERISTICS ≤ 889874AK PRELIMINARY D IFFERENTIAL , V = 3.3V±10% 2.5V±5 2.5V±5 -40°C 85° ≥ ÷ ÷ ÷ ÷ < ≥ www.icst.com/products/hiperclocks.html 5 ICS889874 - -LVPECL UFFER = -40°C 85° < REV. A MARCH 20, 2006 1:2 IVIDER ...

Page 6

... PART 2 Qy tsk(pp ART TO ART KEW 80% Clock 20% Outputs UTPUT ISE ALL IME nIN IN t nRESET HOLD t SET-UP S & ETUP OLD IME 889874AK PRELIMINARY D IFFERENTIAL M I EASUREMENT NFORMATION V CC SCOPE Qx nIN nQx IFFERENTIAL NPUT nQx Qx nQy UTPUT KEW nIN 80 20% nQ0, nQ1 ...

Page 7

... IN/nIN I IGURE I ER LOCK NPUT WITH 50Ω Ω Ω Ω Ω UILT IN RIVEN BY AN 889874AK PRELIMINARY D IFFERENTIAL A I PPLICATION NFORMATION 50Ω Ω Ω Ω Ω ERMINATIONS NTERFACE by the most common driver types. The input interfaces suggested here are examples only. If the driver is from an- ...

Page 8

... IGURE I ER LOCK NPUT WITH 50Ω Ω Ω Ω Ω UILT IN RIVEN BY AN 889874AK PRELIMINARY D IFFERENTIAL 50Ω Ω Ω Ω Ω ERMINATIONS NTERFACE driven by the most common driver types. The input interfaces suggested here are examples only. If the driver is from an- ...

Page 9

... Figure 4. 2. IFFERENTIAL NPUT WITH To prevent oscillation and to reduce noise recommended to have pullup and pulldown connect to true and compliment of the unused input as shown in Figure 5. 889874AK PRELIMINARY D IFFERENTIAL 50Ω Ω Ω Ω Ω UILT N ERMINATION NUSED 3 ...

Page 10

... RTT = – 2)) – 6A. LVPECL O IGURE UTPUT 889874AK PRELIMINARY D IFFERENTIAL O P NPUT AND UTPUT INS O : UTPUTS LVPECL O UTPUT All unused LVPECL outputs can be left floating. We recommend that there is no trace attached. Both sides of the differential output pair should either be left floating or terminated ...

Page 11

... F 7A. 2.5V LVPECL D T IGURE RIVER VCC=2. Ohm Ohm 2,5V LVPECL Driv 7C. 2.5V LVPECL T IGURE ERMINATION 889874AK PRELIMINARY D IFFERENTIAL UTPUT close to ground level. The R3 in Figure 7B can be eliminated and the termination is shown in Figure 7C very CC VCC=2.5V 2.5V R3 250 + 2,5V LVPECL Driv ...

Page 12

... VS IR LOW ABLE FOR JA Multi-Layer PCB, JEDEC Standard Test Boards T C RANSISTOR OUNT The transistor count for ICS889874 is: 326 Pin compatible with SY89874U 889874AK PRELIMINARY D IFFERENTIAL R I ELIABILITY NFORMATION 16 L VFQFN EAD θ θ θ θ θ 0 Air Flow (Linear Feet per Minute) JA 51.5° ...

Page 13

... Integrated Circuit Systems, Inc ACKAGE UTLINE UFFIX FOR Ind ex Area View D Chamfer 4x 0.6 x 0.6 max OPTIONAL T ABLE Reference Document: JEDEC Publication 95, MO-220 889874AK PRELIMINARY D IFFERENTIAL VFQFN EAD S eating Plan Anvil Singula tion (Ref.) N & N Odd ACKAGE IMENSIONS www.icst.com/products/hiperclocks.html 13 ICS889874 - -LVPECL UFFER IVIDER (Ref ...

Page 14

... Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 889874AK PRELIMINARY D ...

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