87949AYILF IDT, Integrated Device Technology Inc, 87949AYILF Datasheet

87949AYILF

Manufacturer Part Number

87949AYILF

Description

Manufacturer

IDT, Integrated Device Technology Inc

Type

Clock Dividerr

Datasheet

1.87949AYILF.pdf (13 pages)

Specifications of 87949AYILF

Number Of Clock Inputs

Output Frequency

160MHz

Output Logic Level

LVCMOS/LVTTL

Operating Supply Voltage (min)

Operating Supply Voltage (typ)

3.3V

Operating Supply Voltage (max)

3.6V

Package Type

LQFP

Operating Temp Range

-40C to 85C

Operating Temperature Classification

Industrial

Mounting

Surface Mount

Pin Count

Lead Free Status / RoHS Status

Compliant

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87949AYI

The ICS87949I is a low skew, ÷1, ÷2 Clock Generator.

The ICS87949I has selectable single ended clock or

LVPECL clock inputs. The single ended clock input

accepts LVCMOS or LVTTL input levels. The PCLK, nPCLK

pair can accept LVPECL, CML, or SSTL input levels. The

low impedance LVCMOS outputs are designed to drive 50Ω

series or parallel terminated transmission lines.The

effective fanout can be increased from 15 to 30 by utilizing

the ability of the outputs to drive two series terminated lines.

The divide select inputs, DIV_SELx, control the output

frequency of each bank. The outputs can be utilized in the

÷1, ÷2 or a combination of ÷1 and ÷2 modes. The master

reset input, MR/nOE, resets the internal frequency dividers

and also controls the active and high impedance states of

all outputs.

The ICS87949I is characterized at 3.3V core/3.3V output.

Guaranteed output and part-to-part skew characteristics make

the ICS87949I ideal for those clock distribution applications

demanding well defined performance and repeatability.

PCLK_SEL

DIV_SELC

DIV_SELD

DIV_SELA

DIV_SELB

CLK_SEL

MR/nOE

LOCK

ENERAL

nPCLK

PCLK

CLK0

CLK1

IAGRAM

ESCRIPTION

÷1

÷2

QA0:QA1

QB0:QB2

QC0:QC3

QD0:QD5

www.idt.com

• Fifteen single ended LVCMOS outputs,

• Selectable LVCMOS or LVPECL clock inputs

• CLK0 and CLK1 can accept the following input levels:

• PCLK, nPCLK supports the following input types:

• Maximum output frequency: 160MHz

• Output skew: 350ps (maximum)

• Part-to-part skew: 2.75ns (maximum)

• 3.3V supply voltage

• -40°C to 85°C ambient operating temperature

• Available in both standard and lead-free RoHS compliant

PCLK_SEL

DIV_SELC

DIV_SELD

DIV_SELA

DIV_SELB

CLK_SEL

7Ω typical output impedance

LVCMOS and LVTTL

LVPECL, CML, SSTL

packages

EATURES

MR/nOE

nPCLK

PCLK

CLK0

CLK1

GND

SSIGNMENT

10mm x 10mm x 1.4mm package body

52 51 50 49 48 47 46 45 44 43 42 41 40

14 15 16 17 18 19 20 21 22 23 24 25 26

52-Lead LQFP

ICS87949I

Y Package

Top View

LOCK

ICS87949I

KEW

REV. C AUGUST 5, 2010

ENERATOR

, ÷1, ÷2

GND

QC0

QC1

GND

QC2

QC3

GND

QD5

DDC

Related parts for 87949AYILF

87949AYILF Summary of contents

Page 1

G D ENERAL ESCRIPTION The ICS87949I is a low skew, ÷1, ÷2 Clock Generator. The ICS87949I has selectable single ended clock or LVPECL clock inputs. The single ended clock input accepts LVCMOS or LVTTL input levels. The PCLK, nPCLK pair ...

Page 2

ABLE IN ESCRIPTIONS ...

Page 3

ABLE IN HARACTERISTICS ...

Page 4

BSOLUTE AXIMUM ATINGS Supply Voltage Inputs Outputs, V DDx Package Thermal Impedance, θ JA Storage Temperature, T STG T 4A ABLE OWER UPPLY HARACTERISTICS ...

Page 5

ABLE HARACTERISTICS ...

Page 6

P ARAMETER 1.65V±0.15V DDx LVCMOS GND -1.65V±0.15V 3. UTPUT OAD EST IRCUIT V DDx DDx sk( UTPUT KEW 2.0V Clock 0.8V Outputs t ...

Page 7

R U ECOMMENDATIONS FOR NUSED I : NPUTS CLK I : NPUT For applications not requiring the use of a clock input, it can be left floating. Though not required, but for additional protection, a 1kΩ resistor can be tied ...

Page 8

LVPECL LOCK NPUT NTERFACE The PCLK /nPCLK accepts LVPECL, CML, SSTL and other differential signals. Both V and V SWING V and V input requirements. Figures show PP CMR interface examples for the PCLK/nPCLK ...

Page 9

ABLE VS IR LOW ABLE FOR JA Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards NOTE: Most modern PCB designs use multi-layered boards. The data in the second row ...

Page 10

ACKAGE UTLINE UFFIX FOR EAD ABLE ...

Page 11

ABLE RDERING NFORMATION ...

Page 12

...

Page 13

We’ve Got Your Timing Solution. 6024 Silver Creek Valley Road San Jose, CA 95138 © 2010 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, the IDT logo, ICS and HiPerClockS are trademarks of ...

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