IDTMPC941FAR2 IDT, Integrated Device Technology Inc, IDTMPC941FAR2 Datasheet - Page 10

IDTMPC941FAR2

Manufacturer Part Number
IDTMPC941FAR2
Description
Manufacturer
IDT, Integrated Device Technology Inc
Type
Clock Driverr
Datasheet

Specifications of IDTMPC941FAR2

Number Of Clock Inputs
2
Output Frequency
250MHz
Output Logic Level
LVCMOS
Operating Supply Voltage (min)
2.375V
Operating Supply Voltage (typ)
2.5/3.3V
Operating Supply Voltage (max)
3.465V
Package Type
LQFP
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Signal Type
LVCMOS/LVPECL
Mounting
Surface Mount
Pin Count
48
Quiescent Current
5mA
Lead Free Status / RoHS Status
Not Compliant
IDT™ / ICS™ CLOCK DISTRIBUTION CHIP
MPC941
LOW VOLTAGE, 1:27 CLOCK DISTRIBUTION CHIP
PCLK_CLK
PCLK_CLK
The time from the PLL controlled edge to the non controlled
edge, divided by the time between PLL controlled edges,
expressed as a percentage
Figure 18. Output Transition Time Test Reference
Figure 14. LVPECL Propagation Delay (t
Q
t
F
Figure 16. Output Duty Cycle (DC)
Figure 12. LVCMOS_CLK MPC941 AC Test Reference for V
t
P
V
Figure 13. PECL_CLK MPC941 AC Test Reference for V
PP
t
PD
Test Reference
Differential Pulse
t
0
Generator
Generator
Z = 50Ω
Z = 50Ω
DC = t
Pulse
P
t
/t
R
0
V
x 100%
CC
0.55
2.4
= 3.3 V V
Z
O
Z
= 50Ω
O
V
CC
V
V
GND
= 50Ω
TT
CC
CC
1.8 V
0.6 V
PD
= 2.5 V
R
V
V
GND
V
R
CC
CC
÷ 2
T
)
CMR
T
= 50Ω
= 50Ω
÷2
V
TT
10
DUT MPC941
DUT MPC941
LVCMOS_CLK
Figure 19. Input Transition Time Test Reference
The pin-to-pin skew is defined as the worst case difference
in propagation delay between any two similar delay path
within a single device
Figure 15. LVCMOS Propagation Delay (t
t
F
Figure 17. Output-to-Output Skew t
Q
CC
CC
= 3.3 V and V
Z
= 3.3 V and V
O
Z
= 50Ω
O
= 50Ω
Test Reference
t
PD
R
R
T
T
= 50Ω
= 50Ω
CC
CC
= 2.5 V
t
SK(O)
V
t
R
= 2.5 V
TT
MPC941 REV. 8 APRIL 29, 2008
V
TT
V
CC
2.0
0.8
= 3.3 V V
SK(O)
CC
1.7 V
0.7 V
PD
= 2.5 V
V
V
GND
V
V
GND
)
V
V
GND
V
V
GND
CC
CC
OH
CC
CC
CC
CC
CC
÷ 2
÷ 2
÷ 2
÷ 2

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