UJA1065TW/3V0-T NXP Semiconductors, UJA1065TW/3V0-T Datasheet - Page 19

Network Controller & Processor ICs HI SPEED CAN SYSTEM

UJA1065TW/3V0-T

Manufacturer Part Number
UJA1065TW/3V0-T
Description
Network Controller & Processor ICs HI SPEED CAN SYSTEM
Manufacturer
NXP Semiconductors
Datasheet

Specifications of UJA1065TW/3V0-T

Number Of Transceivers
1
Power Down Mode
Standby
Operating Supply Voltage (min)
5.5V
Supply Current
10mA
Operating Temperature (max)
125C
Operating Temperature (min)
-40C
Operating Temperature Classification
Automotive
Mounting
Surface Mount
Product
Controller Area Network (CAN)
Data Rate
20 Kbps
Supply Voltage (max)
27 V, 52 V
Supply Voltage (min)
5.5 V
Supply Current (max)
10 mA
Maximum Operating Temperature
+ 125 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Package / Case
HTSSOP EP
Lead Free Status / RoHS Status
Compliant
Other names
UJA1065TW/3V0,518
NXP Semiconductors
UJA1065_7
Product data sheet
6.7.1 Mode control
6.7 CAN transceiver
The integrated high-speed CAN transceiver of the UJA1065 is an advanced ISO 11898-2
and ISO 11898-5 compliant transceiver. In addition to standard high-speed CAN
transceivers the UJA1065 transceiver provides the following features:
The controller of the CAN transceiver provides four modes of operation: Active mode,
On-line mode, On-line Listen mode and Off-line mode; see
In the Diagnosis register two dedicated CAN status bits (CANMD) are available to signal
the mode of the transceiver.
Enhanced error handling and reporting of bus and RXD/TXD failures; these failures
are separately identified in the System Diagnosis register
Integrated autonomous control system for determining the mode of the CAN
transceiver
Ground shift detection with two selectable warning levels, to detect possible local
ground problems before the CAN communication is affected
On-line Listen mode with global wake-up message filter allows partial networking
Bus connections are truly floating when power is off
Rev. 07 — 25 February 2010
High-speed CAN/LIN fail-safe system basis chip
Figure
8.
UJA1065
© NXP B.V. 2010. All rights reserved.
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