LFXP2-17E-6QN208C Lattice, LFXP2-17E-6QN208C Datasheet - Page 37
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LFXP2-17E-6QN208C
Manufacturer Part Number
LFXP2-17E-6QN208C
Description
IC DSP 17KLUTS 146I/O 208PQFP
Manufacturer
Lattice
Datasheet
1.LFXP2-40E-5FN484I.pdf
(92 pages)
Specifications of LFXP2-17E-6QN208C
Number Of Logic Elements/cells
*
Number Of Labs/clbs
*
Total Ram Bits
282624
Number Of I /o
146
Number Of Gates
-
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
*
Operating Temperature
0°C ~ 85°C
Package / Case
*
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
220-1119
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LFXP2-17E-6QN208C
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
Lattice Semiconductor
DQSXFER
LatticeXP2 devices provide a DQSXFER signal to the output buffer to assist it in data transfer to DDR memories
that require DQS strobe be shifted 90
DQSXFER signal runs the span of the data bus.
sysIO Buffer
Each I/O is associated with a flexible buffer referred to as a sysIO buffer. These buffers are arranged around the
periphery of the device in groups referred to as banks. The sysIO buffers allow users to implement the wide variety
of standards that are found in today’s systems including LVCMOS, SSTL, HSTL, LVDS and LVPECL.
sysIO Buffer Banks
LatticeXP2 devices have eight sysIO buffer banks for user I/Os arranged two per side. Each bank is capable of sup-
porting multiple I/O standards. Each sysIO bank has its own I/O supply voltage (V
voltage references, V
shows the eight banks and their associated supplies.
In LatticeXP2 devices, single-ended output buffers and ratioed input buffers (LVTTL, LVCMOS and PCI) are pow-
ered using V
pendent of V
Each bank can support up to two separate V
enced input buffers. Some dedicated I/O pins in a bank can be configured to be a reference voltage supply pin.
Each I/O is individually configurable based on the bank’s supply and reference voltages.
Figure 2-32. LatticeXP2 Banks
CCIO
CCIO
. LVTTL, LVCMOS33, LVCMOS25 and LVCMOS12 can also be set as fixed threshold inputs inde-
.
REF1
V
V REF1(7)
V REF2(7)
V CCIO6
V REF1(6)
V REF2(6)
CCIO7
GND
GND
and V
REF2
, that allow it to be completely independent from the others. Figure 2-32
o
. This shifted DQS strobe is generated by the DQSDEL block. The
REF
Bank 0
Bank 5
voltages, V
BOTTOM
2-34
TOP
REF1
Bank 1
Bank 4
and V
REF2
LatticeXP2 Family Data Sheet
, that set the threshold for the refer-
CCIO
V CCIO2
V REF1(2)
V REF2(2)
V CCIO3
V REF1(3)
V REF2(3)
GND
GND
). In addition, each bank has
Architecture