LFE3-35EA-6FN672I Lattice, LFE3-35EA-6FN672I Datasheet - Page 32
LFE3-35EA-6FN672I
Manufacturer Part Number
LFE3-35EA-6FN672I
Description
IC FPGA 33.3KLUTS 310I/O 672BGA
Manufacturer
Lattice
Datasheet
1.LFE3-150EA-7FN672C.pdf
(136 pages)
Specifications of LFE3-35EA-6FN672I
Number Of Logic Elements/cells
*
Number Of Labs/clbs
*
Total Ram Bits
1358848
Number Of I /o
310
Number Of Gates
-
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
*
Operating Temperature
-40°C ~ 100°C
Package / Case
*
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
220-1082
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LFE3-35EA-6FN672I
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
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Figure 2-31. MULTADDSUBSUM Slice 1
Advanced sysDSP Slice Features
Cascading
The LatticeECP3 sysDSP slice has been enhanced to allow cascading. Adder trees are implemented fully in sys-
DSP slices, improving the performance. Cascading of slices uses the signals CIN, COUT and C Mux of the slice.
Addition
The LatticeECP3 sysDSP slice allows for the bypassing of multipliers and cascading of adder logic. High perfor-
mance adder functions are implemented without the use of LUTs. The maximum width adders that can be imple-
mented are 54-bit.
Rounding
The rounding operation is implemented in the ALU and is done by adding a constant followed by a truncation oper-
ation. The rounding methods supported are:
• Rounding to zero (RTZ)
• Rounding to infinity (RTI)
• Dynamic rounding
• Random rounding
• Convergent rounding
DSP Slice
Previous
IR = Input Register
PR = Pipeline Register
OR = Output Register
FR = Flag Register
Rounding
SRIB
SRIA
C_ALU
A_ALU
CIN
0
IR
C
IR
AA
MULTA
PR
OR
AMUX
A_ALU
IR
From FPGA Core
AB
To FPGA Core
0
R = Logic (B, C)
R= A ± B ± C
2-29
OR
PR
IR
OPCODE
FR
0
=
=
B_ALU
BMUX
IR
ALU
BA
MULTB
OR
PR
LatticeECP3 Family Data Sheet
IR
BB
IR
COUT
SROB
SROA
DSP Slice
Next
Architecture
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