LFE3-150EA-6FN1156I Lattice, LFE3-150EA-6FN1156I Datasheet - Page 73

• Manufacturer Part Number: LFE3-150EA-6FN1156I
• Description: IC FPGA 149KLUTS 586I/O 1156BGA
• Manufacturer: Lattice

Specifications of LFE3-150EA-6FN1156I

• Number Of Logic Elements/cells: *
• Number Of Labs/clbs: *
• Total Ram Bits: 7014400
• Number Of I /o: 586
• Number Of Gates: -
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: *
• Operating Temperature: -40°C ~ 100°C
• Package / Case: *
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 220-1099

Lattice Semiconductor
LatticeECP3 External Switching Characteristics (Continued)
f
t
t
f
Top Side Using PCLK Pin for Clock Input
t
t
f
t
t
f
t
t
f
t
t
f
Generic DDRX2 Inputs with Clock and Data (>10bits wide) are Aligned at Pin (GDDRX2_RX.ECLK.Aligned)
(No CLKDIV)
Left and Right Sides Using DLLCLKPIN for Clock Input
t
t
f
t
t
fMAX_GDDR
t
t
f
t
t
f
Top Side Using PCLK Pin for Clock Input
t
t
f
t
t
f
t
t
MAX_GDDR
DVACLKGDDR
DVECLKGDDR
MAX_GDDR
DVACLKGDDR
DVECLKGDDR
MAX_GDDR
DVACLKGDDR
DVECLKGDDR
MAX_GDDR
DVACLKGDDR
DVECLKGDDR
MAX_GDDR
DVACLKGDDR
DVECLKGDDR
MAX_GDDR
DVACLKGDDR
DVECLKGDDR
MAX_GDDR
DVACLKGDDR
DVECLKGDDR
DVACLKGDDR
DVECLKGDDR
MAX_GDDR
DVACLKGDDR
DVECLKGDDR
MAX_GDDR
DVACLKGDDR
DVECLKGDDR
MAX_GDDR
DVACLKGDDR
DVECLKGDDR
MAX_GDDR
DVACLKGDDR
DVECLKGDDR
Parameter
DDRX2 Clock Frequency
Data Setup Before CLK
Data Hold After CLK
DDRX2 Clock Frequency
Data Setup Before CLK
Data Hold After CLK
DDRX2 Clock Frequency
Data Setup Before CLK
Data Hold After CLK
DDRX2 Clock Frequency
Data Setup Before CLK
Data Hold After CLK
DDRX2 Clock Frequency
Data Setup Before CLK
Data Hold After CLK
DDRX2 Clock Frequency
Data Setup Before CLK
Data Hold After CLK
DDRX2 Clock Frequency
Data Setup Before CLK
Data Hold After CLK
DDRX2 Clock Frequency
Data Setup Before CLK
Data Hold After CLK
DDRX2 Clock Frequency
Data Setup Before CLK 
(Left and Right Sides)
Data Hold After CLK
DDRX2 Clock Frequency
Data Setup Before CLK
Data Hold After CLK
DDRX2 Clock Frequency
Data Setup Before CLK
Data Hold After CLK
DDRX2 Clock Frequency
Data Setup Before CLK
Data Hold After CLK
Over Recommended Commercial Operating Conditions
Description
ECP3-35EA
ECP3-17EA
ECP3-17EA
ECP3-17EA
ECP3-150EA
ECP3-150EA
ECP3-150EA
ECP3-70EA/95EA
ECP3-70EA/95EA
ECP3-70EA/95EA
ECP3-35EA
ECP3-35EA
ECP3-35EA
ECP3-17EA
ECP3-17EA
ECP3-17EA
ECP3-150EA
ECP3-150EA
ECP3-150EA
ECP3-70EA/95EA
ECP3-70EA/95EA
ECP3-70EA/95EA
ECP3-35EA
ECP3-35EA
ECP3-35EA
ECP3-17EA
ECP3-17EA
ECP3-17EA
ECP3-150EA
ECP3-150EA
ECP3-150EA
ECP3-70EA/95EA
ECP3-70EA/95EA
ECP3-70EA/95EA
ECP3-35EA
ECP3-35EA
3-20
Device
DC and Switching Characteristics
0.790
0.775
0.775
0.790
0.790
0.775
0.775
0.790
0.790
0.775
0.775
0.790
Min. Max. Min. Max. Min. Max.
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
LatticeECP3 Family Data Sheet
-8
0.210
0.225
0.225
0.210
0.210
0.225
0.225
0.210
0.210
0.225
0.225
0.210
460
460
235
235
235
235
460
460
460
460
235
235
—
—
—
—
—
—
—
—
—
—
—
—
0.790
0.775
0.775
0.790
0.790
0.775
0.775
0.790
0.790
0.775
0.775
0.790
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
-7
0.210
0.225
0.225
0.210
0.210
0.225
0.225
0.210
0.210
0.225
0.225
0.210
1, 2
385
385
170
170
170
170
385
385
385
385
170
170
—
—
—
—
—
—
—
—
—
—
—
—
0.775
0.790
0.775
0.790
0.790
0.775
0.775
0.790
0.790
0.775
0.775
0.790
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
-6
0.210
0.225
0.225
0.210
0.210
0.225
0.225
0.210
0.210
0.225
0.225
0.210
311
311
130
130
130
130
345
311
311
311
130
130
—
—
—
—
—
—
—
—
—
—
—
—
Units
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
UI
UI
UI
UI
UI
UI
UI
UI
UI
UI
UI
UI
UI
UI
UI
UI
UI
UI
UI
UI
UI
UI
UI
UI