LC4064V-10TN44I Lattice, LC4064V-10TN44I Datasheet - Page 4
LC4064V-10TN44I
Manufacturer Part Number
LC4064V-10TN44I
Description
IC PLD 64MC 30I/O 10NS 44TQFP
Manufacturer
Lattice
Series
ispMACH®r
Datasheet
1.LC4256V-75FTN256BC.pdf
(99 pages)
Specifications of LC4064V-10TN44I
Programmable Type
CPLD
Number Of Macrocells
64
Voltage - Input
3 V ~ 3.6 V
Speed
10ns
Mounting Type
*
Package / Case
*
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
220-1042
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LC4064V-10TN44I
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
Lattice Semiconductor
Figure 2. Generic Logic Block
AND Array
The programmable AND Array consists of 36 inputs and 83 output product terms. The 36 inputs from the GRP are
used to form 72 lines in the AND Array (true and complement of the inputs). Each line in the array can be con-
nected to any of the 83 output product terms via a wired-AND. Each of the 80 logic product terms feed the logic
allocator with the remaining three control product terms feeding the Shared PT Clock, Shared PT Initialization and
Shared PT OE. The Shared PT Clock and Shared PT Initialization signals can optionally be inverted before being
fed to the macrocells.
Every set of five product terms from the 80 logic product terms forms a product term cluster starting with PT0.
There is one product term cluster for every macrocell in the GLB. Figure 3 is a graphical representation of the AND
Array.
from GRP
36 Inputs
4
Generator
Clock
ispMACH 4000V/B/C/Z Family Data Sheet
To GRP
1+OE
1+OE
1+OE
1+OE
1+OE
1+OE
1+OE
1+OE
Output Enable
Product Term
Sharing
To