LCMXO2-1200HC-4MG132CR1 Lattice, LCMXO2-1200HC-4MG132CR1 Datasheet
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LCMXO2-1200HC-4MG132CR1
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LCMXO2-1200HC-4MG132CR1 Summary of contents
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MachXO2™ Family Data Sheet Preliminary DS1035 Version 01.2, April 2011 ...
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... Programmable pull-up or pull-down mode © 2011 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. ...
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... Ultra high I/O device. 2. Contact your Lattice sales representative for the software tool support of these devices/packages. High performance with regulator – High performance without regulator – Low power without regulator – ...
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... JTAG test access port or through the I external Flash memory) and remote field upgrade (TransFR) capability. Lattice provides a variety of design tools that allow complex designs to be efficiently implemented using the MachXO2 family of devices. Popular logic synthesis tools provide synthesis library support for MachXO2. Lattice design tools use the synthesis tool output along with the user-specified preferences and constraints to place and route the design in the MachXO2 device ...
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... EBR blocks. © 2011 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. ...
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... Lattice Semiconductor The logic blocks, Programmable Functional Unit (PFU) and sysMEM EBR blocks, are arranged in a two-dimen- sional grid with rows and columns. Each row has either the logic blocks or the EBR blocks. The PIO cells are located at the periphery of the device, arranged into banks. The PFU contains the building blocks for logic, arithme- tic, RAM, ROM, and register functions ...
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... Lattice Semiconductor Slices Slices 0-3 contain two LUT4s feeding two registers. Slices 0-2 can be configured as distributed memory. Table 2-1 shows the capability of the slices in PFU blocks along with the operation modes they enable. In addition, each PFU contains logic that allows the LUTs to be combined to perform functions such as LUT5, LUT6, LUT7 and LUT8. ...
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... Lattice Semiconductor Table 2-2. Slice Signal Descriptions Function Type Input Data signal Input Data signal Input Multi-purpose Input Control signal Input Control signal Input Control signal Input Inter-PFU signal Output Data signals Output Data signals Output Data signals Output Data signals ...
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... MachXO2 devices support distributed memory initialization. The Lattice design tools support the creation of a variety of different size memories. Where appropriate, the soft- ware will construct these using distributed memory primitives that represent the capabilities of the PFU. Table 2-3 shows the number of slices required to implement different distributed RAM primitives ...
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... Lattice Semiconductor The eight primary clock lines in the primary clock network drive throughout the entire device and can provide clocks for all resources within the device including PFUs, EBRs and PICs. In addition to the primary clock signals, MachXO2 devices also have eight secondary high fanout signals which can be used for global control signals, such as clock enables, synchronous or asynchronous clears, presets, output enables, etc ...
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... Lattice Semiconductor Eight secondary high fanout nets are generated from eight 8:1 muxes as shown in Figure 2-6. One of the eight inputs to the secondary high fanout net input mux comes from dual function clock pins and the remaining seven come from internal routing. ...
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... Lattice Semiconductor The LOCK signal is asserted when the PLL determines it has achieved lock and de-asserted if a loss of lock is detected. A block diagram of the PLL is shown in Figure 2-7. The setup and hold times of the device can be improved by programming a phase shift into the CLKOS, CLKOS2, and CLKOS3 output clocks which will advance or delay the output clock with reference to the CLKOP output clock ...
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... Lattice Semiconductor Table 2-4 provides signal descriptions of the PLL block. Table 2-4. PLL Signal Descriptions Port Name I/O CLKI I CLKFB I PHASESEL[1:0] I PHASEDIR I PHASESTEP I CLKOP O CLKOS O CLKOS2 O CLKOS3 O LOCK O DPHSRC O STDBY I RST I RESETM I RESETC I RESETD I ENCLKOP I ENCLKOS I ENCLKOS2 I ENCLKOS3 I PLLCLK I PLLRST I PLLSTB ...
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... By preloading the RAM block during the chip configuration cycle and disabling the write controls, the sysMEM block can also be utilized as a ROM. Memory Cascading Larger and deeper blocks of RAM can be created using EBR sysMEM Blocks. Typically, the Lattice design tools cascade memory transparently, based on specific design inputs. Single, Dual, Pseudo-Dual Port and FIFO Modes Figure 2-8 shows the five basic memory configurations and their input/output names ...
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... Lattice Semiconductor Figure 2-8. sysMEM Memory Primitives AD[12:0] DI[8:0] CLK CE OCE EBR DO[8:0] RST WE CS[2:0] Single-Port RAM DI[17:0] CLKW WE RST FULLI CSW[1:0] Table 2-6. EBR Signal Descriptions Port Name CLK Clock CE Clock Enable 1 OCE Output Clock Enable RST Reset 1 BE Byte Enable ...
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... Lattice Semiconductor The EBR memory supports three forms of write behavior for single or dual port operation: 1. Normal – Data on the output appears only during the read cycle. During a write cycle, the data (at the current address) does not appear on the output. This mode is supported for all data widths. ...
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... Lattice Semiconductor For further information on the sysMEM EBR block, please refer to TN1201, Devices. EBR Asynchronous Reset EBR asynchronous reset or GSR (if used) can only be applied if all clock enables are low for a clock cycle before the reset is applied and released a clock cycle after the reset is released, as shown in Figure 2-10. The GSR input to the EBR is always asynchronous ...
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... Lattice Semiconductor Figure 2-11. Group of Four Programmable I/O Cells 1 PIC Core Logic/ Routing Notes: 1. Input gearbox is available only in PIC on the bottom edge of MachXO2-640U, MachXO2-1200/U and larger devices. 2. Output gearbox is available only in PIC on the top edge of MachXO2-640U, MachXO2-1200/U and larger devices. Input Register ...
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... Lattice Semiconductor PIO The PIO contains three blocks: an input register block, output register block and tri-state register block. These blocks contain registers for operating in a variety of modes along with the necessary clock and selection logic. Table 2-8. PIO Signal List Pin Name ...
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... Lattice Semiconductor Figure 2-12. MachXO2 Input Register Block Diagram (PIO on Left, Top and Bottom Edges) Programmable D Delay Cell SCLK Right Edge The input register block on the right edge is a superset of the same block on the top, bottom, and left edges. In addition to the modes described above, the input register block on the right edge also supports DDR memory mode ...
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... Lattice Semiconductor In DDR generic mode, D0 and D1 inputs are fed into registers on the positive edge of the clock. At the next falling edge the registered D1 input is registered into the register Q1. A multiplexer running off the same clock is used to switch the mux between the outputs of registers Q0 and Q1 that will then feed the output. ...
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... Lattice Semiconductor Figure 2-15. MachXO2 Output Register Block Diagram (PIO on the Right Edges SCLK DQSW90 TD Tri-state Register Block The tri-state register block registers tri-state control signals from the core of the device before they are passed to the sysIO buffers. The block contains a register for SDR operation. In SDR, TD input feeds one of the flip-flops that then feeds the output ...
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... Lattice Semiconductor These gearboxes have three stage pipeline registers. The first stage registers sample the high-speed input data by the high-speed edge clock on its rising and falling edges. The second stage registers perform data alignment based on the control signals UPDATE and SEL0 from the control block. The third stage pipeline registers pass the data to the device core synchronized to the low-speed system clock ...
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... Lattice Semiconductor More information on the input gearbox is available in TN1203, Devices. Output Gearbox Each PIC on the top edge has a built-in 8:1 output gearbox. Each of these output gearboxes may be programmed as a 7:1 serializer or as one ODDRX4 (8:1) gearbox or as two ODDRX2 (4:1) gearboxes. Table 2-10 shows the gearbox signals ...
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... Lattice Semiconductor Figure 2-17. Output Gearbox ODDRx2_C CDN ODDRx2_A ODDRx2_C SCLK SEL /0 UPDATE ECLK0/1 More information on the output gearbox is available in TN1203, MachXO2 Devices. DDR Memory Support Certain PICs on the right edge of MachXO2-640U, MachXO2-1200/U and larger devices, have additional circuitry to allow the implementation of DDR memory interfaces. There are two groups PIOs each on the right edge with additional circuitry to implement DDR memory interfaces ...
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... Lattice Semiconductor Block, to facilitate the generation of clock and control signals (DQSR90, DQSW90, DDRCLKPOL and DATAVALID). These clock and control signals are distributed to the other PIO in the group through dedicated low skew routing. DQS Read Write Block Source synchronous interfaces generally require the input clock to be adjusted in order to correctly capture data at the input register ...
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... Lattice Semiconductor and differential input termination. The PCI clamp is enabled after V and the device has been configured. 3. Top sysIO Buffer Pairs The sysIO buffer pairs in the top bank of the device consist of two single-ended output drivers and two single- ended input buffers (for ratioed inputs such as LVCMOS and LVTTL). The I/O pairs on the top also have differ- ential and referenced I/O buffers ...
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... Lattice Semiconductor Single-ended buffers with Types of Output Buffers complementary outputs (all I/O banks) Differential Output Emulation All I/O banks Capability PCI Clamp Support No Table 2-12. Supported Input Standards Input Standard Single-Ended Interfaces LVTTL LVCMOS33 LVCMOS25 LVCMOS18 LVCMOS15 LVCMOS12 1 PCI SSTL18 (Class I, Class II) ...
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... Lattice Semiconductor Table 2-13. Supported Output Standards Output Standard Single-Ended Interfaces LVTTL LVCMOS33 LVCMOS25 LVCMOS18 LVCMOS15 LVCMOS12 LVCMOS33, Open Drain LVCMOS25, Open Drain LVCMOS18, Open Drain LVCMOS15, Open Drain LVCMOS12, Open Drain PCI33 SSTL25 (Class I) SSTL18 (Class I) HSTL18(Class I) Differential Interfaces 1, 2 LVDS ...
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... Lattice Semiconductor Figure 2-18. MachXO2-1200U, MachXO2-2000/U, MachXO2-4000 and MachXO2-7000 Banks VCCIO5 GND VCCIO4 GND VCCIO3 GND Figure 2-19. MachXO2-256, MachXO2-640/U and MachXO2-1200 Banks VCCIO3 GND MachXO2 Family Data Sheet GND VCCIO0 Bank 0 VCCIO1 GND Bank 2 GND VCCIO2 GND VCCIO0 Bank 0 VCCIO1 ...
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... Lattice Semiconductor Hot Socketing The MachXO2 devices have been carefully designed to ensure predictable behavior during power-up and power- down. Leakage into I/O pins is controlled to within specified limits. This allows for easy integration with the rest of the system. These capabilities make the MachXO2 ideal for many multiple power supply and hot-swap applica- tions ...
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... Lattice Semiconductor Figure 2-20. Embedded Function Block Interface Core Logic/ Routing 2 Hardened Core Every MachXO2 device contains two I two cores can be configured either cores is that the primary core has pre-assigned I/O pins whereas users can assign I/O pins for the secondary core. ...
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... Lattice Semiconductor 2 Figure 2-21 Core Block Diagram Core Logic/ Routing Table 2-15 describes the signals interfacing with the I 2 Table 2-15 Core Signal Description Signal Name I/O SCLI I SCLO O SCLOEN O SDAI I SDAO O SDAOEN O IRQO O Hardened SPI IP Core Every MachXO2 device has a hard SPI IP core that can be configured as a SPI master or slave. When the IP core is configured as a master it will be able to control other SPI enabled chips connected to the SPI bus ...
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... Lattice Semiconductor Figure 2-22. SPI Core Block Diagram Core Logic/ Routing Table 2-16 describes the signals interfacing with the I Table 2-16. SPI Core Signal Description Signal Name I/O SPI_CSN[0] O SPI_CSN[1..7] O SPI_SCSN I SPI_IRQ O SPI_CLK I/O SPI_MISO I/O SPI_MOSI I/O Hardened Timer/Counter MachXO2 devices provide a hard Timer/Counter IP core ...
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... Lattice Semiconductor • Auto reload • Time-stamping support on the input capture unit • Waveform generation on the output • Glitch-free PWM waveform generation with variable PWM period • Internal WISHBONE bus access to the control and status registers • Stand-alone mode with preloaded control registers and direct reset input Figure 2-23 ...
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... Lattice Semiconductor For more information on the UFM, please refer to TN1205, tions in MachXO2 Devices. Standby Mode and Power Saving Options MachXO2 devices are available in three options for maximum flexibility: ZE, HC and HE devices. The ZE devices have ultra low static and dynamic power consumption. These devices use a 1.2V core voltage that further reduces power consumption ...
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... CCINT CC voltage in addition to the POR circuit that monitors the internal post- CC and V CCINT CCIO supply dropping below Boundary Scan Testability with Lattice sysIO Capability 2-33 Architecture MachXO2 Family Data Sheet level specified in PORUP supply voltage. For devices with CC REFRESH CCINT level (with the PORDNSRAM voltage levels ...
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... Lattice design software uses proprietary compression technology to compress bit-streams for use in MachXO2 devices. Use of this technology allows Lattice to provide a lower cost solution. In the unlikely event that this technol- ogy is unable to compress bitstreams to fit into the amount of on-chip Flash memory, there are a variety of tech- niques that can be utilized to allow the bitstream to fit in the on-chip Flash memory ...
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... Lattice Semiconductor are factory-programmed. The TraceID is accessible through the EFB WISHBONE interface and can also be 2 accessed through the SPI JTAG interfaces. Density Shifting The MachXO2 family has been designed to enable density migration within the same package. Furthermore, the architecture ensures a high success rate when performing design migration from lower density devices to higher density devices ...
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... DC and Switching Characteristics LCMXO2 ZE/HE (1.2V) document is required. 1 Parameter and V are both the same voltage, they must also be the same CCIO CC power supply on boards. CC Condition 3-1 Preliminary Data Sheet DS1035 LCMXO2 HC (2.5V/3.3V) Min. Max. Units 1.14 1.26 V 2.375 3.465 V 1.14 3.465 V ° 0 ...
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... ESD Performance Pin Group All Pins All Pins Lattice qualifies devices per the Human Body Model (HBM) and Charged Device Model (CDM). JEDEC specifica- tions are followed for product qualifications. For more details please refer to the device qualification report Parameter and V ...
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... Lattice Semiconductor DC Electrical Characteristics Symbol Parameter Input or I/O Leakage I/O Active Pull-up Current PU I/O Active Pull-down I PD Current Bus Hold Low sustaining I BHLS current Bus Hold High sustaining I BHHS current Bus Hold Low Overdrive I BHLO current Bus Hold High Overdrive I BHHO ...
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... I DCBG I DCPOR I DCIOBANKCONTROLLER DC and Switching Characteristics Device LCMXO2-256ZE LCMXO2-640ZE LCMXO2-1200ZE LCMXO2-2000ZE LCMXO2-4000ZE LCMXO2-7000ZE 5 All devices Power Estimation and Management for MachXO2 Parameter Bandgap DC power contribution POR DC power contribution DC power contribution per I/O bank controller 3-4 MachXO2 Family Data Sheet 4 Typ. Units 16 µ ...
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... LCMXO2-1200UHC LCMXO2-2000HC LCMXO2-2000UHC LCMXO2-4000HC LCMXO2-7000HC LCMXO2-2000HE LCMXO2-4000HE LCMXO2-7000HE 5 All devices Power Estimation and Management for MachXO2 Device LCMXO2-256ZE LCMXO2-640ZE LCMXO2-1200ZE LCMXO2-2000ZE LCMXO2-4000ZE LCMXO2-7000ZE 6 All devices Power Estimation and Management for MachXO2 or GND and all outputs are tri-stated. 3-5 DC and Switching Characteristics ...
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... Does not include pull-up/pull-down. CCIO Device LCMXO2-256HC LCMXO2-640HC LCMXO2-640UHC LCMXO2-1200HC LCMXO2-1200UHC LCMXO2-2000HC LCMXO2-2000UHC LCMXO2-4000HC LCMXO2-7000HC LCMXO2-2000HE LCMXO2-2000UHE LCMXO2-4000HE LCMXO2-7000HE 6 All devices Power Estimation and Management for MachXO2 or GND and all outputs are tri-stated. 3-6 DC and Switching Characteristics MachXO2 Family Data Sheet Typ ...
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... Lattice Semiconductor sysIO Recommended Operating Conditions Standard Min. LVCMOS 3.3 3.135 LVCMOS 2.5 2.375 LVCMOS 1.8 1.71 LVCMOS 1.5 1.425 LVCMOS 1.2 1.14 LVTTL 3.135 3 PCI 3.135 SSTL25 2.375 SSTL18 1.71 HSTL18 1. LVDS25 2.375 1, 2 LVDS33 3.135 1 LVPECL 3.135 1 BLVDS 2.375 ...
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... Lattice Semiconductor sysIO Single-Ended DC Electrical Characteristics V IL Input/Output Standard Min. (V) Max. (V) LVCMOS 3.3 -0.3 LVTTL LVCMOS 2.5 -0.3 LVCMOS 1.8 -0.3 0.35V LVCMOS 1.5 -0.3 0.35V LVCMOS 1.2 -0.3 0.35V PCI -0.3 0.3V SSTL25 Class I -0.3 V REF SSTL25 Class II -0.3 V REF SSTL18 Class I -0 ...
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... Lattice Semiconductor sysIO Differential Electrical Characteristics The LVDS differential output buffers are available on the top side of MachXO2-640U, MachXO2-1200/U and higher density devices in the MachXO2 PLD family. LVDS Parameter Symbol Parameter Description Input Voltage INP INM V Differential Input Threshold THD V Input Common Mode Voltage ...
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... Lattice Semiconductor LVDS Emulation MachXO2 devices can support LVDS outputs via emulation (LVDS25E). The output is emulated using complemen- tary LVCMOS outputs in conjunction with resistors across the driver outputs on all devices. The scheme shown in Figure 3-1 is one possible solution for LVDS standard implementation. Resistor values in Figure 3-1 are industry standard values for 1% resistors ...
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... Lattice Semiconductor BLVDS The MachXO2 family supports the BLVDS standard through emulation. The output is emulated using complemen- tary LVCMOS outputs in conjunction with resistors across the driver outputs. The input standard is supported by the LVDS differential input buffer. BLVDS is intended for use when multi-drop and bi-directional multi-point differen- tial signaling is required ...
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... Lattice Semiconductor LVPECL The MachXO2 family supports the differential LVPECL standard through emulation. This output standard is emu- lated using complementary LVCMOS outputs in conjunction with resistors across the driver outputs on all the devices. The LVPECL input standard is supported by the LVDS differential input buffer. The scheme shown in Dif- ferential LVPECL is one possible solution for point-to-point signals ...
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... Lattice Semiconductor RSDS The MachXO2 family supports the differential RSDS standard. The output standard is emulated using complemen- tary LVCMOS outputs in conjunction with resistors across the driver outputs on all the devices. The RSDS input standard is supported by the LVDS differential input buffer. The scheme shown in Figure 3-4 is one possible solu- tion for RSDS standard implementation ...
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... Lattice Semiconductor Typical Building Block Function Performance – HC/HE Devices Pin-to-Pin Performance (LVCMOS25 12mA Drive) Function Basic Functions 16-bit decoder 4:1 MUX 16:1 MUX Register-to-Register Performance Function Basic Functions 16:1 MUX 16-bit adder 16-bit counter 64-bit counter Embedded Memory Functions 1024x9 True-Dual Port RAM ...
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... Derating Logic Timing Logic timing provided in the following sections of the data sheet and the Lattice design tools are worst case num- bers in the operating range. Actual delays may be much faster. Lattice design tools can provide logic timing num- bers at a particular temperature and voltage ...
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... Lattice Semiconductor MachXO2 External Switching Characteristics – HC/HE Devices Parameter Description Pin-LUT-Pin Propagation Delay Best case propagation t PD delay through one LUT-4 General I/O Pin Parameters (using Primary Clock without PLL) Clock to Output - PIO t CO Output Register Clock to Data Setup - t SU ...
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... Lattice Semiconductor Parameter Description General I/O Pin Parameters (using Edge Clock without PLL) Clock to Output - PIO t COE Output Register Clock to Data Setup - t SUE PIO Input Register Clock to Data Hold - PIO t HE Input Register Clock to Data Setup - t PIO Input Register with SU_DELE ...
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... Lattice Semiconductor Generic DDRX1 Inputs with Clock and Data Aligned at Pin (GDDRX1_RX.SCLK.Aligned) Using PCLK Pin for Clock Input Parameter Description t Input Data Valid After CLK DVA t Input Data Hold After CLK DVE f DDRX1 Input Data Speed DATA f DDRX1 SCLK Frequency DDRX1 Generic DDRX1 Inputs with Clock and Data Centered at Pin ...
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... Lattice Semiconductor Generic DDRX4 Inputs with Clock and Data Aligned at Pin (GDDRX4_RX.ECLK.Aligned) Using PCLK Pin for Clock Input Parameter Description t Input Data Valid After ECLK DVA t Input Data Hold After ECLK DVE f DDRX4 Serial Input Data Speed DATA f DDRX4 ECLK Frequency ...
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... Lattice Semiconductor Generic DDR Outputs with Clock and Data Centered at Pin (GDDRX1_TX.SCLK.Centered) Using PCLK Pin for Clock Input Parameter Description t Output Data Valid Before CLK Output DVB t Output Data Valid After CLK Output DVA f DDRX1 Output Data Speed DATA DDRX1 SCLK Frequency ...
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... Lattice Semiconductor Generic DDRX4 Outputs with Clock and Data Centered at Pin (GDDRX4_TX.ECLK.Centered) Using PCLK Pin for Clock Input Parameter Description t Output Data Valid Before CLK Output DVB t Output Data Valid After CLK Output DVA f DDRX4 Serial Output Data Speed DATA ...
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... MEM DDR2 Data Transfer Rate MEM_DDR2 1. Commercial timing numbers are shown. Industrial numbers are typically slower and can be extracted from the Lattice design tools. 2. General I/O timing numbers based on LVCMOS 2.5, 8mA, 0pf load. 3. Generic DDR timing numbers based on LVDS I/O. ...
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... Lattice Semiconductor MachXO2 External Switching Characteristics – ZE Devices Parameter Description Pin-LUT-Pin Propagation Delay Best case propagation t PD delay through one LUT-4 General I/O Pin Parameters (using Primary Clock without PLL) Clock to Output - PIO t CO Output Register Clock to Data Setup - t SU PIO Input Register ...
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... Lattice Semiconductor Parameter Description General I/O Pin Parameters (using Edge Clock without PLL) Clock to Output - PIO t COE Output Register Clock to Data Setup - t SUE PIO Input Register Clock to Data Hold - PIO t HE Input Register Clock to Data Setup - t PIO Input Register with SU_DELE ...
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... Lattice Semiconductor Generic DDRX1 Inputs with Clock and Data Aligned at Pin (GDDRX1_RX.SCLK.Aligned) Using PCLK Pin for Clock Input Parameter Description t Input Data Valid After CLK DVA t Input Data Hold After CLK DVE f DDRX1 Input Data Speed DATA f DDRX1 SCLK Frequency DDRX1 Generic DDRX1 Inputs with Clock and Data Centered at Pin ...
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... Lattice Semiconductor Generic DDRX4 Inputs with Clock and Data Aligned at Pin (GDDRX4_RX.ECLK.Aligned) Using PCLK Pin for Clock Input Parameter Description t Input Data Valid After ECLK DVA t Input Data Hold After ECLK DVE f DDRX4 Serial Input Data Speed DATA f DDRX4 ECLK Frequency ...
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... Lattice Semiconductor Generic DDR Outputs with Clock and Data Centered at Pin (GDDRX1_TX.SCLK.Centered) Using PCLK Pin for Clock Input Parameter Description t Output Data Valid Before CLK Output DVB t Output Data Valid After CLK Output DVA f DDRX1 Output Data Speed DATA DDRX1 SCLK Frequency ...
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... Lattice Semiconductor Generic DDRX4 Outputs with Clock and Data Centered at Pin (GDDRX4_TX.ECLK.Centered) Using PCLK Pin for Clock Input Parameter Description t Output Data Valid Before CLK Output DVB t Output Data Valid After CLK Output DVA f DDRX4 Serial Output Data Speed DATA ...
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... MEM DDR2 Data Transfer Rate MEM_DDR2 1. Commercial timing numbers are shown. Industrial numbers are typically slower and can be extracted from the Lattice design tools. 2. General I/O timing numbers based on LVCMOS 2.5, 8mA, 0pf load. 3. Generic DDR timing numbers based on LVDS I/O. ...
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... Lattice Semiconductor Figure 3-6. Receiver RX.CLK.Centered Waveforms RX CLK Input RX Data Input RX.Centered Figure 3-7. Transmitter TX.CLK.Aligned Waveforms TX CLK Output TX Data Output TX.Aligned Figure 3-8. Transmitter TX.CLK.Centered and MEM DDR Output Waveforms TX CLK Output or DQS Output TX Data Output or DQ Output TX.Centered DC and Switching Characteristics ...
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... Lattice Semiconductor Figure 3-9. GDDR71 Video Timing Waveforms 756 Mbps Clock In 125 MHz Data Out 756 Mbps Clock Out 125 MHz Figure 3-10. Receiver GDDR71_RX. Waveforms DC and Switching Characteristics MachXO2 Family Data Sheet 3-31 ...
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... Lattice Semiconductor Figure 3-11. Transmitter GDDR71_TX. Waveforms DC and Switching Characteristics MachXO2 Family Data Sheet 3-32 ...
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... Lattice Semiconductor sysCLOCK PLL Timing Parameter Descriptions f Input Clock Frequency (CLKI, CLKFB) IN Output Clock Frequency (CLKOP, CLKOS, f OUT CLKOS2) f Output Frequency (CLKOS3) OUT2 f PLL VCO Frequency VCO f Phase Detector Input Frequency PFD AC Characteristics t Output Clock Duty Cycle Edge Duty Trim Accuracy ...
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... DC and Switching Characteristics Parameter Device All LCMXO2-256 LCMXO2-640 LCMXO2-1200 LCMXO2-2000 LCMXO2-4000 LCMXO2-7000 All All Device All LCMXO2-256 LCMXO2-640 LCMXO2-640U LCMXO2-1200 LCMXO2-1200U LCMXO2-2000 LCMXO2-2000U LCMXO2-4000 LCMXO2-7000 All STANDBY Mode t PWRDN t WSTDBY 3-34 MachXO2 Family Data Sheet Min. Typ. Max 125.685 133 140.315 124 ...
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... BTUODIS t BSCAN test update register, falling edge of clock to valid enable BTUPOEN DC and Switching Characteristics MachXO2 Family Data Sheet Device Min. LCMXO2-256 LCMXO2-640 LCMXO2-640U LCMXO2-1200 LCMXO2-1200U LCMXO2-2000 LCMXO2-2000U LCMXO2-4000 LCMXO2-7000 Parameter 3-35 Typ. Max. Units 507 µs 722 µs 722 µs 722 µ ...
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... Lattice Semiconductor Figure 3-12. JTAG Port Timing Waveforms TMS TDI t BTCPH TCK TDO Data to be captured from I/O Data to be driven out to I/O DC and Switching Characteristics t t BTS BTH t BTCPL t t BTCO BTCOEN BTCRH t BTCRS Data Captured t t BTUPOEN BUTCO 3-36 ...
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... Lattice Semiconductor sysCONFIG Port Timing Specifications Symbol All Configuration Modes t PRGM t PRGMJ t INITL t DPPINIT t DPPDONE t IODISS Slave SPI f MAX t CCLKH t CCLKL t STSU t STH t STCO t STOZ t STOV t SCS t SCSS t SCSH Master SPI f MAX t MCLKH t MCLKL t STSU t STH t CSSPI t MCLK Port Timing Specifications ...
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... Lattice Semiconductor Switching Test Conditions Figure 3-13 shows the output test load used for AC testing. The specific values for resistance, capacitance, volt- age, and other test conditions are shown in Table 3-5. Figure 3-13. Output Test Load, LVTTL and LVCMOS Standards Table 3-5. Test Fixture Required Components, Non-Terminated Interfaces Test Condition LVTTL and LVCMOS settings (L -> ...
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... Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. ...
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... Lattice Semiconductor Signal Name I/O General Purpose Input Configuration Clock for configuring an FPGA in Slave SPI mode. Output Configuration MCLK/CCLK I/O Clock for configuring an FPGA in SPI and SPIm configuration modes Slave SPI active low chip select input. CSSPIN I/O Master SPI active low chip select output. ...
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... Lattice Semiconductor Pin Information Summary General Purpose I/O per Bank Bank 0 Bank 1 Bank 2 Bank 3 Bank 4 Bank 5 Total General Purpose Single-Ended I/O Differential I/O per Bank Bank 0 Bank 1 Bank 2 Bank 3 Bank 4 Bank 5 Total General Purpose Differential I/O Dual Function I/O High-Speed Differential Outputs (Bank 0) ...
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... Lattice Semiconductor General Purpose I/O per Bank Bank 0 Bank 1 Bank 2 Bank 3 Bank 4 Bank 5 Total General Purpose Single-Ended I/O Differential I/O per Bank Bank 0 Bank 1 Bank 2 Bank 3 Bank 4 Bank 5 Total General Purpose Differential I/O Dual Function I/O High-Speed Differential Outputs (Bank 0) High-Speed Differential Inputs (Bank 2) ...
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... Lattice Semiconductor General Purpose I/O per Bank Bank 0 Bank 1 Bank 2 Bank 3 Bank 4 Bank 5 Total General Purpose Single-Ended I/O Differential I/O per Bank Bank 0 Bank 1 Bank 2 Bank 3 Bank 4 Bank 5 Total General Purpose Differential I/O Dual Function I/O High-Speed Differential Outputs (Bank 0) High-Speed Differential Inputs (Bank 2) ...
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... Lattice Semiconductor General Purpose I/O per Bank Bank 0 Bank 1 Bank 2 Bank 3 Bank 4 Bank 5 Total General Purpose Single-Ended I/O Differential I/O per Bank Bank 0 Bank 1 Bank 2 Bank 3 Bank 4 Bank 5 Total General Purpose Differential I/O Dual Function I/O High-Speed Differential Outputs (Bank 0) High-Speed Differential Inputs (Bank 2) ...
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... Lattice Semiconductor General Purpose I/O per Bank Bank 0 Bank 1 Bank 2 Bank 3 Bank 4 Bank 5 Total General Purpose Single-Ended I/Os Differential I/O per Bank Bank 0 Bank 1 Bank 2 Bank 3 Bank 4 Bank 5 Total General Purpose Differential I/O Dual Function I/O High-Speed Differential Outputs (Bank 0) High-Speed Differential Inputs (Bank 2) ...
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... For further information regarding Thermal Management, refer to the following: • Thermal Management document • TN1198, Power Estimation and Management for MachXO2 Devices • The Power Calculator tool is included with the Lattice design tools standalone download from www.latticesemi.com/software MachXO2 Family Data Sheet 4-8 Pinout Information ...
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... April 2011 MachXO2 Part Number Description LCMXO2 – XXXX – X XXXXXX Device Family MachXO2 PLD Logic Capacity 256 = 256 LUTs 640 = 640 LUTs 1200 = 1280 LUTs 2000 = 2112 LUTs 4000 = 4320 LUTs 7000 = 6864 LUTs I/O Count Blank = Standard Device U = Ultra High I/O Device ...
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... LCMXO2-256ZE-3UMG64C LCMXO2-256ZE-1MG132C LCMXO2-256ZE-2MG132C LCMXO2-256ZE-3MG132C Part Number LCMXO2-640ZE-1TG100C LCMXO2-640ZE-2TG100C LCMXO2-640ZE-3TG100C LCMXO2-640ZE-1MG132C LCMXO2-640ZE-2MG132C LCMXO2-640ZE-3MG132C Part Number LCMXO2-1200ZE-1TG100C LCMXO2-1200ZE-2TG100C LCMXO2-1200ZE-3TG100C LCMXO2-1200ZE-1TG144C LCMXO2-1200ZE-2TG144C LCMXO2-1200ZE-3TG144C LCMXO2-1200ZE-1MG132C LCMXO2-1200ZE-2MG132C LCMXO2-1200ZE-3MG132C Part Number LCMXO2-2000ZE-1TG100C LCMXO2-2000ZE-2TG100C LCMXO2-2000ZE-3TG100C LCMXO2-2000ZE-1TG144C LCMXO2-2000ZE-2TG144C LCMXO2-2000ZE-3TG144C LCMXO2-2000ZE-1MG132C LCMXO2-2000ZE-2MG132C LCMXO2-2000ZE-3MG132C LUTs Supply Voltage Grade 256 1.2V -1 256 1 ...
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... LCMXO2-4000ZE-2TG144C LCMXO2-4000ZE-3TG144C LCMXO2-4000ZE-1MG132C LCMXO2-4000ZE-2MG132C LCMXO2-4000ZE-3MG132C LCMXO2-4000ZE-1BG256C LCMXO2-4000ZE-2BG256C LCMXO2-4000ZE-3BG256C LCMXO2-4000ZE-1FTG256C LCMXO2-4000ZE-2FTG256C LCMXO2-4000ZE-3FTG256C LCMXO2-4000ZE-1BG332C LCMXO2-4000ZE-2BG332C LCMXO2-4000ZE-3BG332C LCMXO2-4000ZE-1FG484C LCMXO2-4000ZE-2FG484C LCMXO2-4000ZE-3FG484C Part Number LCMXO2-7000ZE-1TG144C LCMXO2-7000ZE-2TG144C LCMXO2-7000ZE-3TG144C LCMXO2-7000ZE-1BG256C LCMXO2-7000ZE-2BG256C LCMXO2-7000ZE-3BG256C LCMXO2-7000ZE-1FTG256C LCMXO2-7000ZE-2FTG256C LCMXO2-7000ZE-3FTG256C LCMXO2-7000ZE-1BG332C LCMXO2-7000ZE-2BG332C LCMXO2-7000ZE-3BG332C LCMXO2-7000ZE-1FG484C LCMXO2-7000ZE-2FG484C LCMXO2-7000ZE-3FG484C LUTs Supply Voltage Grade 2112 1.2V -1 2112 1 ...
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... LCMXO2-1200ZE-1MG132CR1 1 LCMXO2-1200ZE-2MG132CR1 1 LCMXO2-1200ZE-3MG132CR1 1. Specifications for the “LCMXO2-1200ZE-speed package CR1” are the same as the “LCMXO2-1200ZE-speed package C” devices respec- tively, except as specified in the R1 Device Specifications section on page 5-15 High-Performance Commercial Grade Devices with Voltage Regulator, Halogen Free (RoHS) Packaging Part Number ...
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... LCMXO2-1200HC-4TG144C LCMXO2-1200HC-5TG144C LCMXO2-1200HC-6TG144C LCMXO2-1200HC-4MG132C LCMXO2-1200HC-5MG132C LCMXO2-1200HC-6MG132C Part Number LCMXO2-1200UHC-4FTG256C LCMXO2-1200UHC-5FTG256C LCMXO2-1200UHC-6FTG256C Part Number LCMXO2-2000HC-4TG100C LCMXO2-2000HC-5TG100C LCMXO2-2000HC-6TG100C LCMXO2-2000HC-4TG144C LCMXO2-2000HC-5TG144C LCMXO2-2000HC-6TG144C LCMXO2-2000HC-4MG132C LCMXO2-2000HC-5MG132C LCMXO2-2000HC-6MG132C LCMXO2-2000HC-4BG256C LCMXO2-2000HC-5BG256C LCMXO2-2000HC-6BG256C LCMXO2-2000HC-4FTG256C LCMXO2-2000HC-5FTG256C LCMXO2-2000HC-6FTG256C Part Number LCMXO2-2000UHC-4FG484C LCMXO2-2000UHC-5FG484C LCMXO2-2000UHC-6FG484C LUTs Supply Voltage Grade 1280 2.5V/3.3V -4 1280 2.5V/3.3V ...
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... LCMXO2-4000HC-4MG132C LCMXO2-4000HC-5MG132C LCMXO2-4000HC-6MG132C LCMXO2-4000HC-4BG256C LCMXO2-4000HC-5BG256C LCMXO2-4000HC-6BG256C LCMXO2-4000HC-4FTG256C LCMXO2-4000HC-5FTG256C LCMXO2-4000HC-6FTG256C LCMXO2-4000HC-4BG332C LCMXO2-4000HC-5BG332C LCMXO2-4000HC-6BG332C LCMXO2-4000HC-4FG484C LCMXO2-4000HC-5FG484C LCMXO2-4000HC-6FG484C Part Number LCMXO2-7000HC-4TG144C LCMXO2-7000HC-5TG144C LCMXO2-7000HC-6TG144C LCMXO2-7000HC-4BG256C LCMXO2-7000HC-5BG256C LCMXO2-7000HC-6BG256C LCMXO2-7000HC-4FTG256C LCMXO2-7000HC-5FTG256C LCMXO2-7000HC-6FTG256C LCMXO2-7000HC-4BG332C LCMXO2-7000HC-5BG332C LCMXO2-7000HC-6BG332C LCMXO2-7000HC-4FG484C LCMXO2-7000HC-5FG484C LCMXO2-7000HC-6FG484C LUTs Supply Voltage Grade 4320 2.5V/3.3V -4 4320 2.5V/3.3V -5 4320 2 ...
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... LCMXO2-1200HC-6TG100CR1 1 LCMXO2-1200HC-4TG144CR1 1 LCMXO2-1200HC-5TG144CR1 1 LCMXO2-1200HC-6TG144CR1 1 LCMXO2-1200HC-4MG132CR1 1 LCMXO2-1200HC-5MG132CR1 1 LCMXO2-1200HC-6MG132CR1 1. Specifications for the “LCMXO2-1200HC-speed package CR1” are the same as the “LCMXO2-1200HC-speed package C” devices respec- tively, except as specified in the R1 Device Specifications section on page 5-15 High-Performance Commercial Grade Devices without Voltage Regulator, Halogen Free ...
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... LCMXO2-4000HE-4FG484C LCMXO2-4000HE-5FG484C LCMXO2-4000HE-6FG484C Part Number LCMXO2-7000HE-4TG144C LCMXO2-7000HE-5TG144C LCMXO2-7000HE-6TG144C LCMXO2-7000HE-4BG256C LCMXO2-7000HE-5BG256C LCMXO2-7000HE-6BG256C LCMXO2-7000HE-4FTG256C LCMXO2-7000HE-5FTG256C LCMXO2-7000HE-6FTG256C LCMXO2-7000HE-4BG332C LCMXO2-7000HE-5BG332C LCMXO2-7000HE-6BG332C LCMXO2-7000HE-4FG484C LCMXO2-7000HE-5FG484C LCMXO2-7000HE-6FG484C Ultra Low Power Industrial Grade Devices, Halogen Free (RoHS) Packaging Part Number LCMXO2-256ZE-1TG100I LCMXO2-256ZE-2TG100I LCMXO2-256ZE-3TG100I LCMXO2-256ZE-1UMG64I LCMXO2-256ZE-2UMG64I LCMXO2-256ZE-3UMG64I LCMXO2-256ZE-1MG132I LCMXO2-256ZE-2MG132I LCMXO2-256ZE-3MG132I ...
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... LCMXO2-640ZE-1MG132I LCMXO2-640ZE-2MG132I LCMXO2-640ZE-3MG132I Part Number LCMXO2-1200ZE-1UWG25ITR LCMXO2-1200ZE-1TG100I LCMXO2-1200ZE-2TG100I LCMXO2-1200ZE-3TG100I LCMXO2-1200ZE-1TG144I LCMXO2-1200ZE-2TG144I LCMXO2-1200ZE-3TG144I LCMXO2-1200ZE-1MG132I LCMXO2-1200ZE-2MG132I LCMXO2-1200ZE-3MG132I Part Number LCMXO2-2000ZE-1UWG49ITR LCMXO2-2000ZE-1TG100I LCMXO2-2000ZE-2TG100I LCMXO2-2000ZE-3TG100I LCMXO2-2000ZE-1TG144I LCMXO2-2000ZE-2TG144I LCMXO2-2000ZE-3TG144I LCMXO2-2000ZE-1MG132I LCMXO2-2000ZE-2MG132I LCMXO2-2000ZE-3MG132I LCMXO2-2000ZE-1BG256I LCMXO2-2000ZE-2BG256I LCMXO2-2000ZE-3BG256I LCMXO2-2000ZE-1FTG256I LCMXO2-2000ZE-2FTG256I LCMXO2-2000ZE-3FTG256I LUTs Supply Voltage Grade 640 1.2V -1 640 1.2V -2 640 1 ...
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... LCMXO2-4000ZE-1MG132I LCMXO2-4000ZE-2MG132I LCMXO2-4000ZE-3MG132I LCMXO2-4000ZE-1BG256I LCMXO2-4000ZE-2BG256I LCMXO2-4000ZE-3BG256I LCMXO2-4000ZE-1FTG256I LCMXO2-4000ZE-2FTG256I LCMXO2-4000ZE-3FTG256I LCMXO2-4000ZE-1BG332I LCMXO2-4000ZE-2BG332I LCMXO2-4000ZE-3BG332I LCMXO2-4000ZE-1FG484I LCMXO2-4000ZE-2FG484I LCMXO2-4000ZE-3FG484I Part Number LCMXO2-7000ZE-1TG144I LCMXO2-7000ZE-2TG144I LCMXO2-7000ZE-3TG144I LCMXO2-7000ZE-1BG256I LCMXO2-7000ZE-2BG256I LCMXO2-7000ZE-3BG256I LCMXO2-7000ZE-1FTG256I LCMXO2-7000ZE-2FTG256I LCMXO2-7000ZE-3FTG256I LCMXO2-7000ZE-1BG332I LCMXO2-7000ZE-2BG332I LCMXO2-7000ZE-3BG332I LCMXO2-7000ZE-1FG484I LCMXO2-7000ZE-2FG484I LCMXO2-7000ZE-3FG484I LUTs Supply Voltage Grade 4320 1.2V -1 4320 1.2V -2 4320 1 ...
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... LCMXO2-1200ZE-1MG132IR1 1 LCMXO2-1200ZE-2MG132IR1 1 LCMXO2-1200ZE-3MG132IR1 1. Specifications for the “LCMXO2-1200ZE-speed package IR1” are the same as the “LCMXO2-1200ZE-speed package I” devices respec- tively, except as specified in the R1 Device Specifications section on page 5-15 High-Performance Industrial Grade Devices with Voltage Regulator, Halogen Free (RoHS) Packaging Part Number ...
Page 97
... LCMXO2-1200HC-4MG132I LCMXO2-1200HC-5MG132I LCMXO2-1200HC-6MG132I Part Number LCMXO2-1200UHC-4FTG256I LCMXO2-1200UHC-5FTG256I LCMXO2-1200UHC-6FTG256I Part Number LCMXO2-2000HC-4TG100I LCMXO2-2000HC-5TG100I LCMXO2-2000HC-6TG100I LCMXO2-2000HC-4TG144I LCMXO2-2000HC-5TG144I LCMXO2-2000HC-6TG144I LCMXO2-2000HC-4MG132I LCMXO2-2000HC-5MG132I LCMXO2-2000HC-6MG132I LCMXO2-2000HC-4BG256I LCMXO2-2000HC-5BG256I LCMXO2-2000HC-6BG256I LCMXO2-2000HC-4FTG256I LCMXO2-2000HC-5FTG256I LCMXO2-2000HC-6FTG256I Part Number LCMXO2-2000UHC-4FG484I LCMXO2-2000UHC-5FG484I LCMXO2-2000UHC-6FG484I Part Number LCMXO2-4000HC-4TG144I LCMXO2-4000HC-5TG144I LCMXO2-4000HC-6TG144I LCMXO2-4000HC-4MG132I 1280 2.5V/3.3V -5 1280 2.5V/3.3V -6 1280 2 ...
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... LCMXO2-4000HC-5MG132I LCMXO2-4000HC-6MG132I LCMXO2-4000HC-4BG256I LCMXO2-4000HC-5BG256I LCMXO2-4000HC-6BG256I LCMXO2-4000HC-4FTG256I LCMXO2-4000HC-5FTG256I LCMXO2-4000HC-6FTG256I LCMXO2-4000HC-4BG332I LCMXO2-4000HC-5BG332I LCMXO2-4000HC-6BG332I LCMXO2-4000HC-4FG484I LCMXO2-4000HC-5FG484I LCMXO2-4000HC-6FG484I Part Number LCMXO2-7000HC-4TG144I LCMXO2-7000HC-5TG144I LCMXO2-7000HC-6TG144I LCMXO2-7000HC-4BG256I LCMXO2-7000HC-5BG256I LCMXO2-7000HC-6BG256I LCMXO2-7000HC-4FTG256I LCMXO2-7000HC-5FTG256I LCMXO2-7000HC-6FTG256I LCMXO2-7000HC-4BG332I LCMXO2-7000HC-5BG332I LCMXO2-7000HC-6BG332I LCMXO2-7000HC-4FG484I LCMXO2-7000HC-5FG484I LCMXO2-7000HC-6FG484I LUTs Supply Voltage Grade 4320 2.5V/3.3V -5 4320 2.5V/3.3V -6 4320 2.5V/3.3V -4 4320 2 ...
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... LCMXO2-1200HC-4MG132IR1 1 LCMXO2-1200HC-5MG132IR1 1 LCMXO2-1200HC-6MG132IR1 1. Specifications for the “LCMXO2-1200HC-speed package IR1” are the same as the “LCMXO2-1200ZE-speed package I” devices respec- tively, except as specified in the R1 Device Specifications section on page 5-15 High Performance Industrial Grade Devices without Voltage Regulator, Halogen Free (RoHS) Packaging Part Number ...
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... R1 Device Specifications “LCMXO2-1200ZE-speed package CR1” devices and “LCMXO2-1200ZE-speed package IR1” devices have the same specifications as “LCMXO2-1200ZE-speed package C” devices and “LCMXO2-1200ZE-speed package I” devices respectively, except as outlined below: • The User Flash Memory (UFM) cannot be programmed through the internal WISHBONE interface. It can still be ...
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... It is recommended to use external termination resistors for differential inputs. The on-chip termination resistors can be disabled through Lattice design software. • SED logic may not produce the correct result when it is run for the first time after configuration. To use this fea- ture, discard the result from the first operation. Subsequent operations will produce the correct result. • ...
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... PCI: www.pcisig.com © 2010 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. ...
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... Characteristics Ordering Information © 2011 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. ...