LCMXO2-1200ZE-1MG132CR1 Lattice, LCMXO2-1200ZE-1MG132CR1 Datasheet - Page 35

• Manufacturer Part Number: LCMXO2-1200ZE-1MG132CR1
• Description: IC PLD 1280LUTS 105I/O 132CSBGA
• Manufacturer: Lattice

Specifications of LCMXO2-1200ZE-1MG132CR1

• Programmable Type: *
• Number Of Macrocells: *
• Voltage - Input: *
• Speed: *
• Mounting Type: *
• Package / Case: *
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 220-1140

Lattice Semiconductor
Figure 2-23. Timer/Counter Block Diagram
Table 2-17. Timer/Counter Signal Description
For more details on these embedded functions, please refer to TN1203,
MachXO2
User Flash Memory (UFM)
MachXO2-640/U and higher density devices provide a User Flash Memory block, which can be used for a variety of
applications including storing a portion of the configuration image, initializing EBRs, to store PROM data or, as a
general purpose user Flash memory. The UFM block connects to the device core through the embedded function
block WISHBONE interface. Users can also access the UFM block through the JTAG, I
device. The UFM block offers the following features:
TCCLKI
TCRSTN
TCIC
TCINT
TCOC
• Auto reload
• Time-stamping support on the input capture unit
• Waveform generation on the output
• Glitch-free PWM waveform generation with variable PWM period
• Internal WISHBONE bus access to the control and status registers
• Stand-alone mode with preloaded control registers and direct reset input
• Non-volatile storage up to 256Kbits
• 100K write cycles
• Write access is performed page-wise; each page has 128 bits (16 bytes).
• Auto-increment addressing
• WISHBONE interface
Port
Devices.
Routing
I/O
Logic
O
O
Core
I
I
I
Timer/Counter input clock signal
Register TC_RSTN_ENA is preloaded by configuration to always keep this pin enabled
Input capture trigger event, applicable for non-pwm modes with WISHBONE interface. If
enabled, a rising edge of this signal will be detected and synchronized to capture TC_CNT value
into TC_ICR for time-stamping.
Without WISHBONE – Can be used as overflow flag
With WISHBONE – Controlled by three IRQ registers
Timer Counter output signal
EFB
WISHBONE
Interface
EFB
Registers
Counter
Timer/
2-31
Description
Timer/Counter
Control
Logic
Implementing High-Speed Interfaces with
MachXO2 Family Data Sheet
2
PWM
C and SPI interfaces of the
Architecture