ICS9FG108DGILFT IDT, Integrated Device Technology Inc, ICS9FG108DGILFT Datasheet - Page 12

• Manufacturer Part Number: ICS9FG108DGILFT
• Description: IC FREQ TIMING GENERATOR 48TSSOP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Frequency Generatorr

Specifications of ICS9FG108DGILFT

• Input: Clock, Crystal
• Output: Differential
• Frequency - Max: 400MHz
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-TSSOP
• Frequency-max: 400MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 800-1259-2; 9FG108DGILFT

IDT
SMBus Table: PLL Frequency Control Register
SMBus Table: PLL Frequency Control Register
SMBus Table: PLL Spread Spectrum Control Register
SMBus Table: PLL Spread Spectrum Control Register
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
ICS9FG108D
Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
TM
Byte 10
Byte 11
Byte 12
Byte 13
Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Pin #
Pin #
Pin #
Pin #
PLL M Div5
PLL M Div4
PLL M Div3
PLL M Div2
PLL M Div1
PLL M Div0
PLL SSP14
PLL SSP13
PLL SSP12
PLL SSP11
PLL SSP10
PLL N Div8
PLL N Div9
PLL N Div7
PLL N Div6
PLL N Div5
PLL N Div4
PLL N Div3
PLL N Div2
PLL N Div1
PLL N Div0
PLL SSP7
PLL SSP6
PLL SSP5
PLL SSP4
PLL SSP3
PLL SSP2
PLL SSP1
PLL SSP0
PLL SSP9
PLL SSP8
Name
Name
Name
Name
M Divider Programming
N Divider Programming
Programming bit(14:8)
Programming bit(7:0)
N Divider Prog bit 8
N Divider Prog bit 9
Byte11 bit(7:0) and
Control Function
Control Function
Control Function
Control Function
Spread Spectrum
Spread Spectrum
Byte10 bit(7:6)
bit (5:0)
Reserved
12
Type
Type
Type
Type
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
N Divider in Byte 11 and
12 will configure the PLL
N Divider in Byte 11 and
12 will configure the PLL
representation of M and
= fXTAL x [NDiv(9:0)+8]
representation of M and
= fXTAL x [NDiv(9:0)+8]
program the spread
program the spread
Byte 13 and 14 will
Byte 13 and 14 will
table. VCO Frequency
table. VCO Frequency
latch-in or Byte 0 Rom
latch-in or Byte 0 Rom
Default at power up =
Default at power up =
pecentage of PLL
pecentage of PLL
Spectrum bits in
Spectrum bits in
These Spread
These Spread
VCO frequency.
VCO frequency.
/ [MDiv(5:0)+2]
/ [MDiv(5:0)+2]
0
0
0
0
The decimal
The decimal
1
1
1
1
Default
Default
Default
Default
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
1542E 12/16/10