ICS557GI-06LF IDT, Integrated Device Technology Inc, ICS557GI-06LF Datasheet - Page 3
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ICS557GI-06LF
Manufacturer Part Number
ICS557GI-06LF
Description
IC CLK BUFFER 1:4 HCSL 20-TSSOP
Manufacturer
IDT, Integrated Device Technology Inc
Type
Clock Bufferr
Datasheet
1.ICS557G-06LF.pdf
(11 pages)
Specifications of ICS557GI-06LF
Input
HCSL, LVDS
Output
HCSL, LVDS
Frequency - Max
200MHz
Voltage - Supply
3.135 V ~ 3.465 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
20-TSSOP
Frequency-max
200MHz
Number Of Clock Inputs
2
Mode Of Operation
Differential
Output Frequency
200MHz
Output Logic Level
HCSL/LVDS
Operating Supply Voltage (min)
3.135V
Operating Supply Voltage (typ)
3.3V
Operating Supply Voltage (max)
3.465V
Package Type
TSSOP
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Signal Type
HCSL/LVDS
Mounting
Surface Mount
Pin Count
20
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
557GI-06LF
800-1068
800-1068-5
800-1068
800-1068
800-1068-5
800-1068
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ICS557GI-06LF
Manufacturer:
IDT
Quantity:
278
Part Number:
ICS557GI-06LFT
Manufacturer:
IDT
Quantity:
20 000
Application Information
Decoupling Capacitors
As with any high-performance mixed-signal IC, the
ICS557-06 must be isolated from system power supply
noise to perform optimally.
Decoupling capacitors of 0.01µF must be connected
between each VDD and the PCB ground plane.
PCB Layout Recommendations
For optimum device performance and lowest output phase
noise, the following guidelines should be observed.
Each 0.01µF decoupling capacitor should be mounted on
the component side of the board as close to the VDD pin as
possible. No vias should be used between decoupling
capacitor and VDD pin. The PCB trace to VDD pin should
be kept as short as possible, as should the PCB trace to the
ground via. Distance of the ferrite bead and bulk decoupling
from the device is less critical.
2) An optimum layout is one with all components on the
same side of the board, minimizing vias through other signal
layers (the ferrite bead and bulk decoupling capacitor can be
mounted on the back). Other signal traces should be routed
away from the ICS557-06.
This includes signal traces just underneath the device, or on
layers adjacent to the ground plane layer used by the device.
IDT® 2 TO 4 DIFFERENTIAL CLOCK MUX
ICS557-06
2 TO 4 DIFFERENTIAL CLOCK MUX
3
External Components
A minimum number of external components are required for
proper operation. Decoupling capacitors of 0.01 μF should
be connected between VDD and GND pairs (2,9 and 15,16)
as close to the device as possible.
Current Reference Source R
If board target trace impedance (Z) is 50Ω , then Rr = 475Ω
(1%), providing IREF of 2.32 mA, output current (I
equal to 6*IREF.
Load Resistors R
Since the clock outputs are open source outputs, 50 ohm
external resistors to ground are to be connected at each
clock output.
Output Termination
The PCI-Express differential clock outputs of the ICS557-06
are open source drivers and require an external series
resistor and a resistor to ground. These resistor values and
their allowable locations are shown in detail in the
PCI-Express Layout Guidelines section.
The ICS557-06 can also be configured for LVDS compatible
voltage levels. See the LVDS Compatible Layout
Guidelines section.
L
r
PCIE FAN OUT BUFFER
(Iref)
ICS557-06
REV J 121510
OH
) is