DS26503L+ Maxim Integrated Products, DS26503L+ Datasheet - Page 5

• Manufacturer Part Number: DS26503L+
• Description: IC T1/E1/J1 BITS ELEMENT 64-LQFP
• Manufacturer: Maxim Integrated Products
• Type: BITS Elementr

Specifications of DS26503L+

• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 64-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Frequency-max: -
• Output: -
• Input: -

DS26503 T1/E1/J1 BITS Element
LIST OF FIGURES
Figure 3-1. Block Diagram ........................................................................................................................11
Figure 3-2. Loopback Mux Diagram (T1/E1 Modes Only) ........................................................................12
Figure 3-3. Transmit PLL Clock Mux Diagram..........................................................................................12
Figure 3-4. Master Clock PLL Diagram ....................................................................................................13
Figure 13-1. Basic Network Connection ...................................................................................................77
Figure 13-2. Typical Monitor Application ..................................................................................................79
Figure 13-3. CMI Coding ..........................................................................................................................81
Figure 13-4. Software-Selected Termination, Metallic Protection.............................................................90
Figure 13-5. Software-Selected Termination, Longitudinal Protection .....................................................91
Figure 13-6. E1 Transmit Pulse Template ................................................................................................92
Figure 13-7. T1 Transmit Pulse Template ................................................................................................92
Figure 13-8. Jitter Tolerance (T1 Mode) ...................................................................................................93
Figure 13-9. Jitter Tolerance (E1 Mode)...................................................................................................93
Figure 13-10. Jitter Attenuation (T1 Mode)...............................................................................................94
Figure 13-11. Jitter Attenuation (E1 Mode) ..............................................................................................94
Figure 16-1. JTAG Functional Block Diagram ..........................................................................................97
Figure 16-2. TAP Controller State Diagram............................................................................................100
Figure 17-1. SPI Serial Port Access, Read Mode, CPOL = 0, CPHA = 0...............................................105
Figure 17-2. SPI Serial Port Access, Read Mode, CPOL = 1, CPHA = 0...............................................105
Figure 17-3. SPI Serial Port Access, Read Mode, CPOL = 0, CPHA = 1...............................................105
Figure 17-4. SPI Serial Port Access, Read Mode, CPOL = 1, CPHA = 1...............................................106
Figure 17-5. SPI Serial Port Access, Write Mode, CPOL = 0, CPHA = 0...............................................106
Figure 17-6. SPI Serial Port Access, Write Mode, CPOL = 1, CPHA = 0...............................................106
Figure 17-7. SPI Serial Port Access, Write Mode, CPOL = 0, CPHA = 1...............................................107
Figure 17-8. SPI Serial Port Access, Write Mode, CPOL = 1, CPHA = 1...............................................107
Figure 19-1. Intel Bus Read Timing (BTS = 0 / BIS[1:0] = 00)...............................................................111
Figure 19-2. Intel Bus Write Timing (BTS = 0 / BIS[1:0] = 00)................................................................111
Figure 19-3. Motorola Bus Timing (BTS = 1 / BIS[1:0] = 00) ..................................................................112
Figure 19-4. Intel Bus Read Timing (BTS = 0 / BIS[1:0] = 01)................................................................114
Figure 19-5. Intel Bus Write Timing (BTS = 0 / BIS[1:0] = 01)................................................................114
Figure 19-6. Motorola Bus Read Timing (BTS = 1 / BIS[1:0] = 01) ........................................................115
Figure 19-7. Motorola Bus Write Timing (BTS = 1 / BIS[1:0] = 01).........................................................115
Figure 19-8. SPI Interface Timing Diagram, CPHA = 0, BIS[1:0] = 10 ...................................................117
Figure 19-9. SPI Interface Timing Diagram, CPHA = 1, BIS[1:0] = 10 ...................................................117
Figure 19-10. Receive Timing, T1/E1 .....................................................................................................118
Figure 19-11. Transmit Timing, T1/E1 ....................................................................................................120
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