IDTCV142PAG8 IDT, Integrated Device Technology Inc, IDTCV142PAG8 Datasheet - Page 15

• Manufacturer Part Number: IDTCV142PAG8
• Description: IC FLEXPC CLK PROGR P4 56-TSSOP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: FlexPC™r
• Type: PC Clockr

Specifications of IDTCV142PAG8

• Input: Crystal
• Output: Clock
• Frequency - Max: 400MHz
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 56-TSSOP
• Frequency-max: 400MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: CV142PAG8

PCI STOP FUNCTIONALITY
programming, they will ignore both the PCI_STOP# pin and the PCI_STOP register bit.
PCI_STOP# - DE-ASSERTION
all PCI[6:0], stoppable PCIF[1:0] and stoppable SRC clocks will resume in a glitch free manner.
PCI_STOP# ASSERTION (TRANSITION FROM ‘1’ TO ‘0’)
clocks will latch low on their next high to low transition. After the PCI clocks are latched low, the SRC clock, (if set to stoppable) will latch high at I
tristate if Byte 2 Bit 6 = 1) upon its next low to high transition and the SRC# will latch low as shown below.
IDTCV142
PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR
PCI_STOP#
The PCI_STOP# signal is on an active low input controlling PCI and SRC outputs. If PCIF[1:0] and SRC clocks can be set to be free-running through SMBus
The de-assertion of the PCI_STOP# signal is to be sampled on the rising edge of the PCIF free running clock domain. After detecting PCI_STOP# de-assertion,
The clock samples the PCI_STOP# signal on a rising edge of PCIF clock. After detecting the PCI_STOP# assertion low, all PCI[6:0] and stoppable PCIF[1:0]
1
0
Normal
Normal
CPU
PCIF[1:0] 33MHz
PCIF[1:0] 33MHz
PCI[6:0] 33MHz
PCI[6:0] 33MHz
SRC# 100MHz
SRC# 100MHz
SRC 100MHz
SRC 100MHz
PCI_STOP#
PCI_STOP#
Normal
Normal
CPU#
I
REF
Normal
* 6 or float
SRC
t
SU
t
SU
Normal
SRC#
Low
t
DRIVE_SRC
15
PCIF/PCI
33MHz
Low
48MHz
48MHz
USB
COMMERCIAL TEMPERATURE RANGE
DOT96
Normal
Normal
DOT96#
Normal
Normal
14.318MHz
14.318MHz
REF
REF
* 6 (or