IDTCV152PVG8 IDT, Integrated Device Technology Inc, IDTCV152PVG8 Datasheet - Page 4

• Manufacturer Part Number: IDTCV152PVG8
• Description: IC FLEXPC CLK PROGR P4 56-SSOP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: FlexPC™r
• Type: PC Clockr

Specifications of IDTCV152PVG8

• Input: Crystal
• Output: Clock
• Frequency - Max: 400MHz
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 56-SSOP
• Frequency-max: 400MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: CV152PVG8

RESOLUTION
INDEX BLOCK WRITE PROTOCOL
INDEX BYTE WRITE
Setting bit[11:18] = starting address, bit[20:27] = 01h.
IDTCV152
PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR
11-18
20-27
29-36
38-45
Bit
2-9
10
19
28
37
46
1
CPU (MHz)
100
133
166
200
266
333
400
# of bits
1
8
1
8
1
8
1
8
1
8
1
Master
Master
Master
Master
Master
Master
Master
Master
From
Slave
Slave
Slave
Slave
Slave
Slave
Resolution
0.666667
0.666667
1.333333
1.333333
1.333333
2.666667
2.666667
Start
D2h
Register offset byte (starting byte)
Byte count, N (0 is not valid)
first data byte (Offset data byte)
2nd data byte
:
Nth data byte
Acknowledge
Stop
Ack (Acknowledge)
Ack (Acknowledge)
Ack (Acknowledge)
Ack (Acknowledge)
Ack (Acknowledge)
Description
N =
150
200
125
150
200
125
150
4
SE SIGNAL STRENGTH SELECTION
INDEX BYTE READ
Setting bit[11:18] = starting address. After reading back the first data byte,
master issues Stop bit.
INDEX BLOCK READ PROTOCOL
Master can stop reading any time by issuing the stop bit without waiting
until Nth byte (byte count bit30-37).
11-18
21-28
30-37
39-46
48-55
Bit
2-9
10
19
20
29
38
47
1
Str[1:0]
# of bits
00
01
10
11
1
8
1
8
1
1
8
1
8
1
8
1
8
Master
Master
Master
Master
Master
Master
Master
Master
Master
From
Slave
Slave
Slave
Slave
Slave
Slave
Slave
Strength
0.6x
0.8x
1x
1.2x
COMMERCIAL TEMPERATURE RANGE
Start
D2h
Ack (Acknowledge)
Register offset byte (starting byte)
Ack (Acknowledge)
Repeated Start
D3h
Ack (Acknowledge)
Byte count, N (block read back of N
Ack (Acknowledge)
first data byte (Offset data byte)
Ack (Acknowledge)
2nd data byte
Ack (Acknowledge)
Ack (Acknowledge)
Nth data byte
Not acknowledge
Stop
bytes), power on is 8
:
Description