IDTCV146PVG IDT, Integrated Device Technology Inc, IDTCV146PVG Datasheet - Page 4
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IDTCV146PVG
Manufacturer Part Number
IDTCV146PVG
Description
IC FLEXPC CLK PROGR P4 56-SSOP
Manufacturer
IDT, Integrated Device Technology Inc
Series
FlexPC™r
Type
PC Clockr
Datasheet
1.IDTCV146PVG8.pdf
(16 pages)
Specifications of IDTCV146PVG
Input
Crystal
Output
Clock
Frequency - Max
400MHz
Voltage - Supply
3.135 V ~ 3.465 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
56-SSOP
Frequency-max
400MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
CV146PVG
PIN DESCRIPTION (CONT.)
INDEX BLOCK WRITE PROTOCOL
INDEX BYTE WRITE
Setting bit[11:18] = starting address, bit[20:27] = 01h.
IDTCV146
PROGRAMMABLE FLEXPC™ CLOCK FOR P4 PROCESSOR
Pin Number
11-18
20-27
29-36
38-45
Bit
2-9
10
19
28
37
46
1
43
44
45
46
47
48
49
50
51
52
53
54
55
56
# of bits
1
8
1
8
1
8
1
8
1
8
1
REF0/ FSC
REF1/ FSA
XTAL_OUT
Master
Master
Master
Master
Master
Master
Master
Master
Slave
Slave
Slave
Slave
Slave
V
From
V
Slave
V
XTAL_IN
V
CPUC1
CPUC0
CPUT1
CPUT0
DD
SS
DD
SS
Name
SDA
SCL
_CPU
_CPU
_REF
_REF
Start
D2h
Ack (Acknowledge)
Register offset byte (starting byte)
Ack (Acknowledge)
Byte count, N (0 is not valid)
Ack (Acknowledge)
first data byte (Offset data byte)
Ack (Acknowledge)
2nd data byte
Ack (Acknowledge)
:
Nth data byte
Acknowledge
Stop
Type
PWR
GND
GND
PWR
OUT
OUT
OUT
OUT
OUT
I/O
I/O
I/O
IN
I N
Description
Host 0.7V current mode differential clock output
Host 0.7V current mode differential clock output
3.3V
Host 0.7V current mode differential clock output
Host 0.7V current mode differential clock output
GND
SM bus clock
SM bus data
Xtal output
Xtal input
GND
14.318 MHz reference clock output. CPU frequency selection at V
14.318 MHz reference clock output. CPU frequency selection at V
3.3V
4
INDEX BLOCK READ PROTOCOL
Master can stop reading any time by issuing the stop bit without waiting
until Nth byte (byte count bit30-37).
INDEX BYTE READ
Setting bit[11:18] = starting address. After reading back the first data byte,
master issues Stop bit.
11-18
21-28
30-37
39-46
48-55
Bit
2-9
10
19
20
29
38
47
1
# of bits
1
8
1
8
1
1
8
1
8
1
8
1
8
Master
Master
Master
Master
Master
Master
Master
Master
Master
From
Slave
Slave
Slave
Slave
Slave
Slave
Slave
Description
COMMERCIAL TEMPERATURE RANGE
Start
D2h
Ack (Acknowledge)
Register offset byte (starting byte)
Ack (Acknowledge)
Repeated Start
D3h
Ack (Acknowledge)
Byte count, N (block read back of N
Ack (Acknowledge)
first data byte (Offset data byte)
Ack (Acknowledge)
2nd data byte
Ack (Acknowledge)
Ack (Acknowledge)
Nth data byte
Not acknowledge
Stop
bytes), power on is 8
:
TT
TT
_P
_P
WRGD
WRGD
Description
# assertion.
# assertion.