VF2510BGT IDT, Integrated Device Technology Inc, VF2510BGT Datasheet

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VF2510BGT

Manufacturer Part Number
VF2510BGT
Description
IC PLL CLK DRIVER 3.3V 24-TSSOP
Manufacturer
IDT, Integrated Device Technology Inc
Type
PLL Clock Driverr
Datasheet

Specifications of VF2510BGT

Input
Clock
Output
Clock
Frequency - Max
200MHz
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
24-TSSOP
Frequency-max
200MHz
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
3.3V Phase-Lock Loop Clock Driver
General Description
The ICSVF2510 is a high performance, low skew, low jitter
clock driver. It uses a phase lock loop (PLL) technology to
align, in both phase and frequency, the CLKIN signal with
the CLKOUT signal. It is specifically designed for use with
synchronous SDRAMs. The ICSVF2510 operates at 3.3V
VCC and drives up to ten clock loads.
One bank of ten outputs provide low-skew, low-jitter
copies of CLKIN. Output signal duty cycles are adjusted
to 50 percent, independent of the duty cycle at CLKIN.
Outputs can be enabled or disabled via control (OE)
inputs. When the OE inputs are high, the outputs align in
phase and frequency with CLKIN; when the OE inputs are
low, the outputs are disabled to the logic low state.
The ICSVF2510 does not require external RC filter
components. The loop filter for the PLL is included on-chip,
minimizing component count, board space, and cost. The
test mode shuts off the PLL and connects the input
directly to the output buffer. This test mode, the ICSVF2510
can be use as low skew fanout clock buffer device. The
ICSVF2510 comes in 24 pin 173mil Thin Shrink Small-
Outline package (TSSOP) package.
Block Diagram
CLKIN
0722B—05/06/04
AVCC
FBIN
OE
Integrated
Circuit
Systems, Inc.
PLL
FBOUT
CLK0
CLK1
CLK2
CLK3
CLK4
CLK5
CLK6
CLK7
CLK8
CLK9
Features
Meets or exceeds PC133 registered DIMM
specification1.1
Spread Spectrum Clock Compatible
Distributes one clock input to one bank of ten outputs
Operating frequency 20MHz to 200MHz
External feedback input (FBIN) terminal is used to
synchrionize the outputs to the clock input
No external RC network required
Operates at 3.3V Vcc
Plastic 24-pin 173mil TSSOP package
Industrial temperature version available
FBOUT 12
AGND 1
CLK0 3
CLK1 4
CLK2 5
CLK3 8
CLK4 9
GND 6
GND 7
VCC 2
VCC 10
Pin Configuration
OE 11
4.40 mm. Body, 0.65 mm. Pitch
24 Pin TSSOP
ICSVF2510
24 CLKIN
23 AVCC
22 VCC
21 CLK9
20 CLK8
19 GND
18 GND
17 CLK7
16 CLK6
15 CLK5
14 VCC
13 FBIN

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VF2510BGT Summary of contents

Page 1

Integrated Circuit Systems, Inc. 3.3V Phase-Lock Loop Clock Driver General Description The ICSVF2510 is a high performance, low skew, low jitter clock driver. It uses a phase lock loop (PLL) technology to align, in both phase and frequency, the CLKIN ...

Page 2

ICSVF2510 Pin Descriptions PIN # PIN NAME TYPE 1 AGND PWR 2, 10, 14 VCC PWR 3 CLK0 OUT 4 CLK1 OUT 5 CLK2 OUT 6, 7, 18, 19 GND PWR 8 CLK3 OUT 9 CLK4 OUT ...

Page 3

Absolute Maximum Ratings Supply Voltage (AVCC AVCC < (V Supply Voltage (VCC ...

Page 4

ICSVF2510 Electrical Characteristics - Input & Supply 70°C; Supply Voltage PARAMETER SYMBOL Input High Voltage V IH Input Low Voltage V IL Input High Current I IH Input Low Current ...

Page 5

PARAMETER MEASUREMENT INFORMATION From Output Under Test 30 pF Figure 1. Load Circuit for Outputs Notes includes probe and jig capacitance All input pulses are supplied by generators having the following characteristics: PRR 133 MHz, Z ...

Page 6

ICSVF2510 General Layout Precautions: An ICS2509C is used as an example similar to the ICSVF2510. The same rules and methods apply. 1) Use copper flooded ground on the top signal layer under the clock buffer The area under ...

Page 7

INDEX INDEX AREA AREA 4.40 mm. Body, 0.65 mm. pitch TSSOP (0.0256 Inch) (173 mil) Ordering Information ICSVF2510yGLF-T Example: ICS XXXX y G LF- T 0722B—05/06/04 c ...

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