ICS95V847AGLF IDT, Integrated Device Technology Inc, ICS95V847AGLF Datasheet - Page 5

no-image

ICS95V847AGLF

Manufacturer Part Number
ICS95V847AGLF
Description
IC CLOCK DRIVER 2.5V 24-TSSOP
Manufacturer
IDT, Integrated Device Technology Inc
Type
Clock Driverr
Series
-r
Datasheet

Specifications of ICS95V847AGLF

Input
Clock
Output
Clock
Frequency - Max
233MHz
Voltage - Supply
2.3 V ~ 2.7 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
24-TSSOP
Frequency-max
233MHz
Number Of Elements
1
Supply Current
148mA
Operating Supply Voltage (typ)
2.5V
Operating Temp Range
0C to 85C
Package Type
TSSOP
Operating Supply Voltage (min)
2.3V
Operating Supply Voltage (max)
2.7V
Operating Temperature Classification
Commercial
Pin Count
24
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
95V847AGLF

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ICS95V847AGLF
Manufacturer:
ICS
Quantity:
1 556
Part Number:
ICS95V847AGLF
Manufacturer:
ICS
Quantity:
20 000
Part Number:
ICS95V847AGLFT
Manufacturer:
ICS
Quantity:
2 056
Notes:
1. Refers to transition on noninverting output in PLL bypass mode.
2.
3. Switching characteristics guaranteed for application frequency range.
4. Static phase offset shifted by design.
0718E—11/24/08
T
Max clock frequency
Application Frequency
Range
Input clock duty cycle
CLK stabilization
Low-to high level
propagation delay time
High-to low level propagation
delay time
Output enable time
Output disable time
Period jitter
Half-period jitter
Input clock slew rate
Output clock slew rate
Cycle to Cycle Jitter
Phase error
Output to Output Skew
Timing Requirements
Switching Characteristics (see note 3)
A
= 0 - 85°C; Supply Voltage A
While the pulse skew is almost constant over frequency, the duty cycle error
increases at higher frequencies. This is due to the formula: duty cycle=t
the cycle (t
PARAMETER
PARAMETER
c
) decreases as the frequency goes up.
1
VDD
t
SYMBOL
SYMBOL
t(jit_hper)
(phase error)
T
freq
T
cyc
freq
T
, V
T
t
t
t
tdis
jit (per)
d
PLH
t
STAB
PLL
t
sl(o)
skew
sl(i)
EN
tin
-T
DD
App
op
1
1
cyc
= 2.5 V +/- 0.2V (unless otherwise stated)
4
2.5V+0.2V @ 25
2.5V+0.2V @ 25
CLK_IN to any output
CLK_IN to any output
PD# to any output
PD# to any output
100MHz to 200MHz
100MHz to 200MHz
100MHz to 200MHz
CONDITIONS
CONDITION
5
o
o
C
C
wH
MIN
45
95
40
/t
MIN
-30
-75
-50
c
1
1
, where
MAX
233
210
60
15
TYP
5.5
5.5
5
5
0
UNITS
MHz
MHz
ICS95V847
µs
%
MAX
2.5
30
30
60
50
60
4
UNITS
V/ns
V/ns
ns
ns
ns
ns
ps
ps
ps
ps
ps

Related parts for ICS95V847AGLF