ICS9DB102BGLF IDT, Integrated Device Technology Inc, ICS9DB102BGLF Datasheet - Page 9

• Manufacturer Part Number: ICS9DB102BGLF
• Description: IC BUFFER PCI EXPRESS 20-TSSOP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Zero Delay Bufferr
• Series: -r

Specifications of ICS9DB102BGLF

• Input: Clock
• Output: HCSL
• Frequency - Max: 101MHz
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 20-TSSOP
• Frequency-max: 101MHz
• Number Of Elements: 1
• Supply Current: 100mA
• Pll Input Freq (min): 80MHz
• Pll Input Freq (max): 105MHz
• Operating Supply Voltage (typ): 3.3V
• Operating Temp Range: 0C to 70C
• Package Type: TSSOP
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (max): 3.465V
• Operating Temperature Classification: Commercial
• Pin Count: 20
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Compliant, Lead free / RoHS Compliant
• Other names: 9DB102BGLF

IDT
SMBus Table: Device Control Register, READ/WRITE ADDRESS (D4/D5)
SMBus Table: Output Enable Register
SMBus Table: Function Select Register
SMBus Table: Vendor & Revision ID Register
ICS9DB102
Two Output Differential Buffer for PCIe Gen1 & Gen2
®
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Two Output Differential Buffer for PCIe Gen1 & Gen2
Byte 0
Byte 1
Byte 2
Byte 3
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Pin #
Pin #
Pin #
Pin #
PLL BW #adjust
PLL Enable
SW_EN
Name
Name
Name
Name
RID3
RID2
RID1
RID0
VID3
VID2
VID1
VID0
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
Control Function Type
Bypasses PLL for
Control Function Type
Control Function Type
Control Function Type
Enables SMBus
REVISION ID
VENDOR ID
Selects PLL
Bandwidth
board test
Control
9
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
R
R
R
R
R
R
R
R
(fan out mode)
PLL bypassed
controlled by
Functions
registers
Low BW
SMBus
0
0
0
0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
controlled by
PLL enabled
(ZDB mode)
device pins
Functions
High BW
1
1
1
1
-
-
-
-
-
-
-
-
PWD
PWD
PWD
PWD
852
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
1
1
1
0
0
0
1
0
0
0
1
REV M 01/27/11