ICS9LPRS365BKLFT IDT, Integrated Device Technology Inc, ICS9LPRS365BKLFT Datasheet - Page 4

• Manufacturer Part Number: ICS9LPRS365BKLFT
• Description: IC CLK SYNTHESIZR CK505 64VFQFPN
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of ICS9LPRS365BKLFT

• Input: *
• Output: *
• Frequency - Max: *
• Voltage - Supply: *
• Operating Temperature: *
• Mounting Type: Surface Mount
• Package / Case: *
• Frequency-max: *
• Number Of Elements: 3
• Supply Current: 250mA
• Pll Input Freq (max): 14.318MHz
• Operating Supply Voltage (typ): 3.3V
• Operating Temp Range: 0C to 70C
• Package Type: VFQFPN EP
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (max): 3.465V
• Operating Temperature Classification: Commercial
• Pin Count: 64
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Compliant, Lead free / RoHS Compliant
• Other names: 9LPRS365BKLFT

TSSOP Pin Description (Continued)
1218—09/01/10
PIN #
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
SRCT11/CR#_H
SRCT10
SRCC10
VDDSRC_IO
CPU_STOP#
PCI_STOP#
VDDSRC
SRCC6
SRCT6
GNDSRC
SRCC7/CR#_E
SRCT7/CR#_F
VDDSRC_IO
CPUC2_ITP/SRCC8
CPUT2_ITP/SRCT8
NC
PIN NAME
TYPE
OUT
OUT
PWR
PWR
OUT
OUT
PWR
PWR
OUT
OUT
N/A
I/O
I/O
I/O
IN
IN
SRC11 true or Clock Request control H for SRC10 pair
The power-up default is SRC11, but this pin may also be used as a Clock Request control of SRC10 via
SMBus. Before configuring this pin as a Clock Request Pin, the SRC11 output pair must first be disabled in
byte 3, bit 7 of SMBus configuration space After the SRC11 output is disabled (high-Z), the pin can then be
set to serve as a Clock Request for SRC10 pair using byte 6, bit 4 of SMBus configuration space
Byte 6, bit 4
0 = SRC11 enabled (default)
1= CR#_H controls SRC10.
True clock of differential SRC clock pair.
Complement clock of differential SRC clock pair.
Stops all CPU Clocks, except those set to be free running clocks. In AMT mode 3 bits are shifted in from
the ICH to set the FSC, FSB, FSA values
Stops all PCI Clocks, except those set to be free running clocks. In AMT mode 3 bits are shifted in from
the ICH to set the FSC, FSB, FSA values
VDD pin for SRC Pre-drivers, 3.3V nominal
Complement clock of low power differential SRC clock pair.
True clock of low power differential SRC clock pair.
Ground for SRC clocks
SRC7 complement or Clock Request control E for SRC6 pair
The power-up default is SRC7#, but this pin may also be used as a Clock Request control of SRC6 via
SMBus. Before configuring this pin as a Clock Request Pin, the SRC7 output pair must first be disabled in
byte 3, bit 3 of SMBus configuration space . After the SRC output is disabled (high-Z), the pin can then be
set to serve as a Clock Request for SRC6 pair using byte 6, bit 7 of SMBus configuration space
Byte 6, bit 7
0 = SRC7# enabled (default)
1= CR#_E controls SRC6.
SRC7 true or Clock Request control 8 for SRC8 pair
The power-up default is SRC7, but this pin may also be used as a Clock Request control of SRC8 via
SMBus. Before configuring this pin as a Clock Request Pin, the SRC7 output pair must first be disabled in
byte 3, bit 3 of SMBus configuration space After the SRC output is disabled (high-Z), the pin can then be
set to serve as a Clock Request for SRC8 pair using byte 6, bit 6 of SMBus configuration space
Byte 6, bit 6
0 = SRC7# enabled (default)
1 = CR#_F controls SRC8.
Complement clock of low power differential CPU2/Complement clock of differential SRC pair. The function
of this pin is determined by the latched input value on pin 7, PCIF5/ITP_EN on powerup. The function is as
follows:
Pin 7 latched input Value
0 = SRC8#
1 = ITP#
True clock of low power differential CPU2/True clock of differential SRC pair. The function of this pin is
determined by the latched input value on pin 7, PCIF5/ITP_EN on powerup. The function is as follows:
Pin 7 latched input Value
0 = SRC8
1 = ITP
No Connect
1.05V to 3.3V from external power supply
1.05V to 3.3V from external power supply
4
DESCRIPTION
ICS9LPRS365
Datasheet