ICS93732AFT IDT, Integrated Device Technology Inc, ICS93732AFT Datasheet
ICS93732AFT
Specifications of ICS93732AFT
Related parts for ICS93732AFT
ICS93732AFT Summary of contents
Page 1
Integrated Circuit Systems, Inc. Low Cost DDR Phase Lock Loop Zero Delay Buffer Recommended Application: DDR Zero Delay Clock Buffer Product Description/Features: • Low skew, low jitter PLL clock driver • Max frequency supported = 266MHz (DDR 533) 2 • ...
Page 2
ICS93732 Pin Descriptions PIN # PIN NAME PIN TYPE DESCRIPTION 1 DDRC0 OUT 2 DDRT0 OUT 3 VDD PWR 4 DDRT1 OUT 5 DDRC1 OUT 6 GND PWR 7 SCLK IN 8 CLK_INT IN 9 N/C N/C 10 VDDA PWR ...
Page 3
Absolute Maximum Ratings Supply Voltage (VDD & AVDD -0.5V to 3.6V Logic Inputs . . . . . . . . . . . . . . . . . ...
Page 4
ICS93732 Timing Requirements 70°C; Supply Voltage AV A PARAMETER SYMBOL freq Operating Clock Frequency 1 d Input Clock Duty Cycle 1 Clock Stabilization t STAB 1. Guaranteed by design, not 100% tested in production. Switching Characteristics ...
Page 5
General I The information in this section assumes familiarity with I For more information, contact ICS for an I How to Write: • Controller (host) sends a start bit. • Controller (host) sends the write address D4 • ICS clock ...
Page 6
ICS93732 Bytes are reseved power up default = 1. This allows operation with main clock. BYTE Affected Pin 5 Pin # Name Bit DDR0(T&C) Bit DDR1(T&C) Bit Bit ...
Page 7
INDEX INDEX AREA AREA 209 mil SSOP Ordering Information ICS93732yFLFT Example: ICS XXXX 0578J—06/20/08 c SYMBOL ...
Page 8
ICS93732 Revision History Rev. Issue Date Description I 5/18/2005 Added LF Ordering Information to TSSOP package. J 6/20/2008 Removed TSSOP Ordering Information. 0578J—06/20/08 8 Page # 8 - ...