MPC96877VKR2 IDT, Integrated Device Technology Inc, MPC96877VKR2 Datasheet - Page 5

• Manufacturer Part Number: MPC96877VKR2
• Description: IC CLK DRIVER 1:10 SDRAM 52-BGA
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: PLL Clock Driverr

Specifications of MPC96877VKR2

• Input: Clock
• Output: SSTL-18
• Frequency - Max: 340MHz
• Voltage - Supply: 1.7 V ~ 1.9 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 52-BGA
• Frequency-max: 340MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

IDT™ 1.8 V PLL 1:10 Differential SDRAM Clock Driver
Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc
MPC96877
1.8 V PLL 1:10 Differential SDRAM Clock Driver
Table 3. Absolute Maximum Ratings Over Free-Air Operating Range
1. Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
2. The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
3. This value is limited to 2.5 V maximum.
Table 4. Recommended Operating Conditions
1. The PLL is turned off and bypassed for test purposes when AV
2. V
FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA
Supply voltage range, V
Input voltage range, V
Output voltage range, V
Input clamp current, I
Output clamp voltage, I
Continuous output current, IO (V
Continuous current through each V
Storage temperature range, T
Output supply voltage
Supply voltage
Low-level input voltage
High-level input voltage
High-level output current
Low-level output current
Input differential-pair cross voltage
Input voltage level
Input differential-pair voltage
(see
Operating free-air temperature
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
operating conditions and not timing parameters are guaranteed.
Output
ID
Figure 9. Half-Period
is the magnitude of the difference between the input level on CK and the input level on CK, see
for definition. For CK and CK the V
1
Rating
IK
I
2, 3
2
OK
(V
2
O
DDQ
1, 2
I
(V
Jitter)
< 0 or V
or AV
2
O
STG
< 0 or V
O
DD
= 0 to V
I
DDQ
> V
O
DDQ
or GND
> V
DDQ
)
DDQ
IH
)
and V
)
Parameter
Parameter
AV
V
V
V
I
I
V
V
V
DDQ
OH
OL
IL
IH
IX
IN
ID
IL
DD
limits are used to define the DC low and high levels for the logic detect state.
OE, OS, CK, CK
OE, OS, CK, CK
Affected Pins
DD
is grounded. During this test mode, V
DC
AC
5
1
(V
0.65 x V
DDQ
Min
–0.3
1.7
0.3
0.6
/2) –0.15
0
DDQ
Figure 12. Time Delay between OE and Clock
DDQ
Nom
V
1.8
DDQ
remains within the recommended
–0.5 V to V
–0.5 V to V
(V
–65°C to 150°C
–0.5 V to 2.5 V
0.35 x V
DDQ
V
V
V
±100 mA
DDQ
DDQ
DDQ
±50 mA
±50 mA
±50 mA
Value
Max
1.9
/2) +0.15
–9
70
9
DDQ
DDQ
+0.3
+0.4
+0.4
DDQ
MPC96877
+ 0.5 V
+ 0.5 V
NETCOM
Unit
mA
mA
°
V
V
V
MPC96877
C
551